Search results for "Xianlong Hong"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Kan Wang, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong	Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong	Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Shan Zeng, Wenjian Yu, Xianlong Hong, Chung-Kuan Cheng	Efficient Power Network Analysis with Modeling of Inductive Effects.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong	Effective congestion reduction for IC package substrate routing.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
1	Yuchun Ma, Qiang Zhou, Pingqiang Zhou, Xianlong Hong	Thermal Impacts of Leakage Power in 2D/3D floorplanning.	Journal of Circuits, Systems, and Computers	2010	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Yin Shen, Qiang Zhou, Yici Cai, Xianlong Hong	ECP- and CMP-Aware Detailed Routing Algorithm for DFM.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong	PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang	Simultaneous slack budgeting and retiming for synchronous circuits optimization.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Shan Zeng, Wenjian Yu, Jin Shi, Xianlong Hong, Chung-Kuan Cheng	Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Yuchun Ma, Xin Li, Yu Wang 0002, Xianlong Hong	Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	A single layer zero skew clock routing in X architecture.	Science in China Series F: Information Sciences	2009	DBLP DOI BibTeX RDF	single layer, X architecture, zero skew, clock routing
1	Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong	Substrate Topological Routing for High-Density Packages.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Qiang Zhou, Xin Zhao, Yici Cai, Xianlong Hong	An MTCMOS technology for low-power physical design.	Integration	2009	DBLP DOI BibTeX RDF
1	Haixia Yan, Qiang Zhou, Xianlong Hong	Thermal aware placement in 3D ICs using quadratic uniformity modeling approach.	Integration	2009	DBLP DOI BibTeX RDF
1	Dawei Liu, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong	Cell shifting aware of wirelength and overlap.	ISQED	2009	DBLP DOI BibTeX RDF
1	Shan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng	Efficient power network analysis with complete inductive modeling.	ISQED	2009	DBLP DOI BibTeX RDF
1	Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong	Simultaneous buffer and interlayer via planning for 3D floorplanning.	ISQED	2009	DBLP DOI BibTeX RDF
1	Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong	Incremental power optimization for multiple supply voltage design.	ISQED	2009	DBLP DOI BibTeX RDF
1	Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong	Modern Floorplanning with Boundary Clustering Constraint.	ISVLSI	2009	DBLP DOI BibTeX RDF
1	Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong	Diffusion-driven congestion reduction for substrate topological routing.	ISPD	2009	DBLP DOI BibTeX RDF	congestion reduction, ic package, substrate routing, diffusion, routability
1	Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto	Integrated interlayer via planning and pin assignment for 3D ICs.	SLIP	2009	DBLP DOI BibTeX RDF
1	Fubing Mao, Yuchun Ma, Ning Xu, Xianlong Hong, Yu Wang 0002	Multi-objective Floorplanning Based on Fuzzy Logic.	FSKD	2009	DBLP DOI BibTeX RDF
1	Xin Li, Yuchun Ma, Xianlong Hong	A novel thermal optimization flow using incremental floorplanning for 3D ICs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Xiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Jacob Relles	An efficient decoupling capacitance optimization using piecewise polynomial models.	DATE	2009	DBLP BibTeX RDF
1	Sheqin Dong, Hongjie Bai, Xianlong Hong, Satoshi Goto	Buffer Planning for 3D ICs.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Hui Dai, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong	Fast placement for large-scale hierarchical FPGAs.	CAD/Graphics	2009	DBLP DOI BibTeX RDF
1	Yanming Jia, Yici Cai, Xianlong Hong	Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong	Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Low Power Gated Clock Tree Driven Placement.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong	Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Yici Cai, Qiang Zhou, Xianlong Hong, Rui Shi, Yang Wang	Application of optical proximity correction technology.	Science in China Series F: Information Sciences	2008	DBLP DOI BibTeX RDF	layout, rules-based, OPC, model-based, IC
1	Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng 0002, Lei He, Xianlong Hong	Fashion: A Fast and Accurate Solution to Global Routing Problem.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Yici Cai, Le Kang, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan	Random Walk Guided Decap Embedding for Power/Ground Network Optimization.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Tom Tong Jing, Yu Hu, Zhe Feng 0002, Xianlong Hong, Xiaodong Hu, Guiying Yan	A full-scale solution to the rectilinear obstacle-avoiding Steiner problem.	Integration	2008	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	Zero skew clock routing in X-architecture based on an improved greedy matching algorithm.	Integration	2008	DBLP DOI BibTeX RDF
1	Yici Cai, Jin Shi, Zhu Pan, Xianlong Hong, Sheldon X.-D. Tan	Large scale P/G grid transient simulation using hierarchical relaxed approach.	Integration	2008	DBLP DOI BibTeX RDF
1	Haixia Yan, Qiang Zhou, Xianlong Hong	Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm.	ISQED	2008	DBLP DOI BibTeX RDF	placement, DCT, 3D, thermal
1	Xiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong	IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization.	ISQED	2008	DBLP DOI BibTeX RDF	interconnect power, piecewise model, slack
1	Yin Shen, Yici Cai, Qiang Zhou, Xianlong Hong	DFM Based Detailed Routing Algorithm for ECP and CMP.	ISQED	2008	DBLP DOI BibTeX RDF	ECP, CMP, DFM, detailed routing
1	Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong	MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation.	FPL	2008	DBLP DOI BibTeX RDF
1	Yibo Wang, Yici Cai, Xianlong Hong	A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Yanming Jia, Yici Cai, Xianlong Hong	Full-chip routing system for reducing Cu CMP & ECP variation.	SBCCI	2008	DBLP DOI BibTeX RDF	electroplating, routing, chemical mechanical polishing
1	Liangpeng Guo, Yici Cai, Qiang Zhou, Le Kang, Xianlong Hong	A novel performance driven power gating based on distributed sleep transistor network.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	physical design, power-gating, sleep transistors
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity and register placement aware gated clock network design.	ISPD	2008	DBLP DOI BibTeX RDF	gated clock tree, low power, placement
1	Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong	Topological routing to maximize routability for package substrate.	DAC	2008	DBLP DOI BibTeX RDF	IC package, substrate routing, system in package
1	Shuai Li, Jin Shi, Yici Cai, Xianlong Hong	Vertical via design techniques for multi-layered P/G networks.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong	Heuristic power/ground network and floorplan co-design method.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian	Low power clock buffer planning methodology in F-D placement for large scale circuit design.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong	LP based white space redistribution for thermal via planning and performance optimization in 3D ICs.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto	Symmetry constraint based on mismatch analysis for analog layout in SOI technology.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong	Leakage power optimization for clock network using dual-Vth technology.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Gate planning during placement for gated clock network.	ICCD	2008	DBLP DOI BibTeX RDF
1	Yibo Wang, Yici Cai, Xianlong Hong, Yi Zou	Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Yici Cai, Bin Liu 0007, Qiang Zhou, Xianlong Hong	Voltage Island Generation in Cell Based Dual-Vdd Design.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Tom Tong Jing, Zhe Feng 0002, Yu Hu, Xianlong Hong, Xiaodong Hu, Guiying Yan	lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With O(nlog n) Complexity.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Jin Shi, Yici Cai, Sheldon X.-D. Tan, Jeffrey Fan, Xianlong Hong	Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng	Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Qiang Zhou, Yici Cai, Duo Li, Xianlong Hong	A Yield-Driven Gridless Router.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	gridless routing, integrated circuit layout, critical area, design for yield
1	Yaoguang Wei, Sheqin Dong, Xianlong Hong	APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement.	Integration	2007	DBLP DOI BibTeX RDF
1	Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu	An efficient quadratic placement based on search space traversing technology.	Integration	2007	DBLP DOI BibTeX RDF
1	Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Partitioning-based decoupling capacitor budgeting via sequence of linear programming.	Integration	2007	DBLP DOI BibTeX RDF
1	Yici Cai, Bin Liu 0007, Jin Shi, Qiang Zhou, Xianlong Hong	Power Delivery Aware Floorplanning for Voltage Island Designs.	ISQED	2007	DBLP DOI BibTeX RDF
1	Hongjie Bai, Sheqin Dong, Xianlong Hong	Congestion Driven Buffer Planning for X-Architecture.	ISQED	2007	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture.	ISQED	2007	DBLP DOI BibTeX RDF
1	Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong	Interconnect Power Optimization Based on Timing Analysis.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Hailong Yao, Yici Cai, Xianlong Hong	CMP-aware Maze Routing Algorithm for Yield Enhancement.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong	An effective buffer planning algorithm for IP based fixed-outline SOC placement.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	buffer planning, very large scale integration (VLSI), floorplanning, fixed-outline
1	Yanming Jia, Yici Cai, Xianlong Hong	Dummy fill aware buffer insertion during routing.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	routing, VLSI, DFM, buffer insertion, dummy fill
1	Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong	New timing and routability driven placement algorithms for FPGA synthesis.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	congestion driven placement, physical synthesis, timing driven placement, net weight
1	Xinjie Wei, Yici Cai, Xianlong Hong	Physical aware clock skew rescheduling.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	skew rescheduling, process variations, clock skew
1	Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma	An accurate and efficient probabilistic congestion estimation model in x architecture.	SLIP	2007	DBLP DOI BibTeX RDF	congestion estimation, dynamic resource assignment, the X architecture, routability
1	Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan	Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach.	ASP-DAC	2007	DBLP DOI BibTeX RDF	programming method, decoupling capacitor budgeting algorithm, random walk approach, decap budgeting algorithm, power ground network design, isolation property, decap optimization process, leakage currents optimization algorithm, refined leakage model, heuristic method
1	Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou	Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.	ASP-DAC	2007	DBLP DOI BibTeX RDF	graph-based approach, microarchitecture pipelining optimization, throughput-aware floorplanning, block pipelining, interconnect pipelining, graph-based algorithm, mixed integer linear programming, wire pipelining
1	Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong	DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang	Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos.	ASP-DAC	2007	DBLP DOI BibTeX RDF	stochastic parameterized model order reduction, Hermite polynomial chaos, stochastic model order reduction algorithm, stochastic Hermite polynomials, stochastic interconnect analysis, nonGaussian input variations, implicit system representation, block matrix structure, Monte Carlo methods, linear equations
1	Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong	Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation.	ASP-DAC	2007	DBLP DOI BibTeX RDF	thermal-optimal placement, thermal-driven symmetry constraint, analog layout, thermal constraint, hot-spot effect, temperature gradient, symmetrical devices, placement process, geometric symmetry, corner block list, thermal model
1	Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong	Logic and Layout Aware Voltage Island Generation for Low Power Design.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Statistical model order reduction for interconnect circuits considering spatial correlations.	DATE	2007	DBLP DOI BibTeX RDF
1	Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai	Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma	A Fast 3D-BSG Algorithm for 3D Packing Problem.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Xinjie Wei, Yici Cai, Xianlong Hong	Effective Acceleration of Iterative Slack Distribution Process.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Haixia Yan, Zhuoyuan Li, Xianlong Hong, Qiang Zhou	Unified Quadratic Programming Approach For 3-D Mixed Mode Placement.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Le Kang, Yici Cai, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan, Xiaoyi Wang	Simultaneous Switching Noise Consideration for Power/Ground Network Optimization.	CAD/Graphics	2007	DBLP DOI BibTeX RDF
1	Pingqiang Zhou, Yuchun Ma, Qiang Zhou, Xianlong Hong	Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning.	CAD/Graphics	2007	DBLP DOI BibTeX RDF
1	Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou	3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Ning Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong	Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani	Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	floorplanning, thermal, 3D IC
1	Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Xiaoyi Wang, Zhu Pan, Jingjing Fu	Time-domain analysis methodology for large-scale RLC circuits and its applications.	Science in China Series F: Information Sciences	2006	DBLP DOI BibTeX RDF	RLC circuits, analog circuit analysis, P/G networks, algorithm complexity, time-domain analysis
1	Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong	Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Xinjie Wei, Yici Cai, Meng Zhao, Xianlong Hong	Legitimate Skew Clock Routing with Buffer Insertion.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	legitimate skew, buffer insertion, clock routing
1	Yici Cai, Bin Liu 0007, Yan Xiong, Qiang Zhou, Xianlong Hong	Priority-Based Routing Resource Assignment Considering Crosstalk.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	track reservation, routing, VLSI, crosstalk, resource assignment
1	Yu Hu, Tong Jing, Zhe Feng 0002, Xianlong Hong, Xiaodong Hu, Guiying Yan	ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	rectilinear Steiner minimal tree (RSMT), routing, physical design, ant colony optimization (ACO)
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu	General Floorplans with L/T-Shaped Blocks Using Corner Block List.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	corner block list, L/T-shaped blocks, floorplanning
1	Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, Jun Gu	A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design.	Integration	2006	DBLP DOI BibTeX RDF
1	Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming.	ISQED	2006	DBLP DOI BibTeX RDF

Publications of "Xianlong Hong" ( http://dblp.L3S.de/Authors/Xianlong_Hong )