Search results for "Xiaoqing Wen"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Hassan Salmani, Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty, Patrick Girard, Xiaoqing Wen	Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns.	J. Low Power Electronics	2012	DBLP BibTeX RDF
1	Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara	A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara	Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu	Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen	Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing.	ITC	2011	DBLP DOI BibTeX RDF
1	Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang	A novel scan segmentation design method for avoiding shift timing failure in scan testing.	ITC	2011	DBLP DOI BibTeX RDF
1	Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich	SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures.	ISLPED	2011	DBLP BibTeX RDF
1	Michael A. Kochte, Sandip Kundu, Kohei Miyase, Xiaoqing Wen, Hans-Joachim Wunderlich	Efficient BDD-based Fault Simulation in Presence of Unknown Values.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel	Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Mohammad Tehranipoor, Rohit Kapur, Anand Bhat, Amitava Majumdar, LeRoy Winemberg	Special session 5B: Panel How much toggle activity should we be testing with?	VTS	2011	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor	Power-aware test generation with guaranteed launch safety for at-speed scan testing.	VTS	2011	DBLP DOI BibTeX RDF
1	Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed	A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor	High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja	A Study of Capture-Safe Test Generation Flow for At-Speed Testing.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Hiroshi Furukawa, Hao-Jan Chao, Boryau Sheu, Jianghao Guo, Wen-Ben Jone	Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed	Is test power reduction through X-filling good enough?	ITC	2010	DBLP DOI BibTeX RDF
1	Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura	On estimation of NBTI-Induced delay degradation.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen	Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes.	DDECS	2010	DBLP DOI BibTeX RDF
1	Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase	Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li	Turbo1500: Core-Based Design for Test and Diagnosis.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara	A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing.	PRDC	2009	DBLP DOI BibTeX RDF
1	Kazunari Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, H. Sone, Seiji Kajihara, M. Aso, Hiroshi Furukawa	CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara	A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment.	ICCAD	2009	DBLP BibTeX RDF
1	C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen	Test Strategies for Low-Power Devices.	J. Low Power Electronics	2008	DBLP DOI BibTeX RDF
1	Kohei Miyase, Kenta Terashima, Xiaoqing Wen, Seiji Kajihara, Sudhakar M. Reddy	On Detection of Bridge Defects with Stuck-at Tests.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Yuta Yamato, Yusuke Nakamura, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara	A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	At-speed scan testing, Capture switching activity, X-filling, Test cube, ATPG, Low power testing
1	Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu	VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF	combinational broadcaster, combinational compactor, fault diagnosis, ATPG, test compression, low-power testing, scan testing
1	Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li	Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard.	ITC	2008	DBLP DOI BibTeX RDF
1	Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase	Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing.	ITC	2008	DBLP DOI BibTeX RDF
1	C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen	Test Strategies for Low Power Devices.	DATE	2008	DBLP DOI BibTeX RDF
1	Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen	Power-Aware Testing and Test Strategies for Low Power Devices.	DATE	2008	DBLP DOI BibTeX RDF
1	Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte	On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.	DFT	2008	DBLP DOI BibTeX RDF
1	Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen	Diagnosis of Realistic Defects Based on the X-Fault Model.	DDECS	2008	DBLP DOI BibTeX RDF
1	Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara	Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita	A Novel ATPG Method for Capture Power Reduction during Scan Testing.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu	At-Speed Logic BIST for IP Cores	CoRR	2007	DBLP BibTeX RDF
1	Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang	A novel scheme to reduce power supply noise for high-quality at-speed scan testing.	ITC	2007	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja	Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing.	DAC	2007	DBLP DOI BibTeX RDF
1	Nicola Nicolici, Xiaoqing Wen	Embedded Tutorial on Low Power Test.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo	Estimation of delay test quality and its application to test generation.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita	A Per-Test Fault Diagnosis Method Based on the X-Fault Model.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	A New Method for Low-Capture-Power Test Generation for Scan Testing.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Yu Hu, Yinhe Han, Xiaowei Li, Huawei Li, Xiaoqing Wen	Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Shohei Morishima, Akane Takuma, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato	A Framework of High-quality Transition Fault ATPG for Scan Circuits.	ITC	2006	DBLP DOI BibTeX RDF
1	Hiroshi Furukawa, Xiaoqing Wen, Laung-Terng Wang, Boryau Sheu, Zhigang Jiang, Shianling Wu	A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing.	ITC	2006	DBLP DOI BibTeX RDF
1	Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato	A dynamic test compaction procedure for high-quality path delay testing.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita	A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.	VTS	2006	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja	Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation.	ICCD	2006	DBLP BibTeX RDF
1	Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja	Efficient Test Set Modification for Capture Power Reduction.	J. Low Power Electronics	2005	DBLP DOI BibTeX RDF
1	Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, Xiaoqing Wen	Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita	On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita	Fault Diagnosis of Physical Defects Using Unknown Behavior Model.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF
1	Yu Hu, Xiaowei Li, Huawei Li, Xiaoqing Wen	Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time.	PRDC	2005	DBLP DOI BibTeX RDF
1	Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau Sheu, Shianling Wu, Shyh-Horng Lin, Ming-Tung Chang	UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction.	ITC	2005	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	Low-capture-power test generation for scan-based at-speed testing.	ITC	2005	DBLP DOI BibTeX RDF
1	Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy	On Improving Defect Coverage of Stuck-at Fault Tests.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato	Path delay test compaction with process variation tolerance.	DAC	2005	DBLP DOI BibTeX RDF	process variation, delay testing, path delay fault, test compaction
1	Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty	Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	On Low-Capture-Power Test Generation for Scan Testing.	VTS	2005	DBLP DOI BibTeX RDF
1	B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, P. Hsu, J. Cho, J. Park, H. Chao, Shianling Wu	At-Speed Logic BIST for IP Cores.	DATE	2005	DBLP DOI BibTeX RDF
1	Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo	At-Speed Logic BIST Architecture for Multi-Clock Designs.	ICCD	2005	DBLP DOI BibTeX RDF
1	Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai	VirtualScan: A New Compressed Scan Technology for Test Cost Reduction.	ITC	2004	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	On per-test fault diagnosis using the X-fault model.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita	Fault Diagnosis for Physical Defects of Unknown Behaviors.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Hsin-Po Wang	A Flexible Logic BIST Scheme and Its Application to SoC Designs. (PDF / PS)	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
1	Hiroshi Yokoyama, Xiaoqing Wen, Hideo Tamamoto	Random pattern testable design with partial circuit duplication and IDDQ testing.	Systems and Computers in Japan	1999	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Tooru Honzawa, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita	Design for Diagnosability of CMOS Circuits.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita	IDDQ test vector selection for transistor short fault testing.	Systems and Computers in Japan	1997	DBLP DOI BibTeX RDF
1	Xiaoqing Wen	Fault Diagnosis for Static CMOS Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF
1	Hiroshi Yokoyama, Xiaoqing Wen, Hideo Tamamoto	Random Pattern Testable Design with Partial Circuit Duplication.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Partial circuit duplication, Random testing Built-in self test, Design for testability
1	Xiaoqing Wen, Kewal K. Saluja	A new method towards achieving global optimality in technology mapping.	ICCAD	1996	DBLP DOI BibTeX RDF	Combinational Logic Synthesis, Optimality, Technology Mapping
1	Xiaoqing Wen, Kozo Kinoshita, Hideo Tamamoto, Hiroshi Yokoyama	Efficient Guided-Probe Fault Location Method for Sequential Circuits.	IEICE Transactions	1995	DBLP BibTeX RDF
1	Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita	Testing of k-FR Circuits under Highly Observable Condition.	IEICE Transactions	1995	DBLP BibTeX RDF
1	Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita	Transistor leakage fault location with ZDDQ measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	field effect transistor circuits, transistor leakage fault location, I/sub DDQ/ measurement, equivalence fault collapsing, diagnosed faults, gate-array circuit, fault diagnosis, logic testing, random tests, fault location, CMOS logic circuits, leakage currents, logic arrays, CMOS circuit, deterministic tests, electric current measurement, diagnostic resolution
1	Xiaoqing Wen, Kozo Kinoshita	A Testable Design of Logic Circuits under Highly Observable Condition.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	highly observable condition, fault tolerant computing, logic testing, integrated circuit testing, combinational circuit, stuck-at faults, logic circuits, integrated logic circuits, combinatorial circuits, stuck-open faults, testable design
1	Xiaoqing Wen, Kozo Kinoshita	Testable Designs of Sequential Circuits Under Highly Observable Condition.	ITC	1992	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kozo Kinoshita	A testable design of logic circuits under highly observable condition.	ITC	1990	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kozo Kinoshita	Fault detection and diagnosis of k-UCP circuits under totally observable condition.	FTCS	1990	DBLP DOI BibTeX RDF

Publications of "Xiaoqing Wen" ( http://dblp.L3S.de/Authors/Xiaoqing_Wen )