Search results for "Xiaoxia Wu"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Xiaoxia Wu, Wei Zhao, Mark Nakamoto, Chandra Nimmagadda, Durodami Lisk, Sam Gu, Riko Radojcic, Matt Nowak, Yuan Xie	Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Feng Wang 0004, Yibo Chen, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan	Variation-Aware Task and Communication Mapping for MPSoC Architecture.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Xiangyu Dong, Xiaoxia Wu, Yuan Xie, Yiran Chen, Hai Helen Li	Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation.	IET Computers & Digital Techniques	2011	DBLP DOI BibTeX RDF
1	Xiaoxia Wu, Jian Li, Lixin Zhang 0002, Evan Speight, Ramakrishnan Rajamony, Yuan Xie	Design exploration of hybrid caches with disparate memory technologies.	TACO	2010	DBLP DOI BibTeX RDF
1	Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie	Test-access mechanism optimization for core-based three-dimensional SOCs.	Microelectronics Journal	2010	DBLP DOI BibTeX RDF
1	Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li	Cost-driven 3D integration with interconnect layers.	DAC	2010	DBLP DOI BibTeX RDF	interconnect service layer, three-dimensional integrated circuit, network-on-chip
1	Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie	Scan-chain design and optimization for three-dimensional integrated circuits.	JETC	2009	DBLP DOI BibTeX RDF	scan-chain design, genetic algorithm, integer linear programming, randomized rounding, LP relaxation, 3D ICs
1	Xiaoxia Wu, Jian Li, Lixin Zhang 0002, Evan Speight, Ramakrishnan Rajamony, Yuan Xie	Hybrid cache architecture with disparate memory technologies.	ISCA	2009	DBLP DOI BibTeX RDF	hybrid cache architecture, three-dimensional ic
1	Guangyu Sun, Xiaoxia Wu, Yuan Xie	Exploration of 3D stacked L2 cache design for high performance and efficient thermal control.	ISLPED	2009	DBLP DOI BibTeX RDF	thermal control, performance, 3D, L2 caches
1	Xiaoxia Wu, Jian Li, Lixin Zhang 0002, Evan Speight, Yuan Xie	Power and performance of read-write aware Hybrid Caches with non-volatile memories.	DATE	2009	DBLP BibTeX RDF
1	Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie	Test-Access Solutions for Three-Dimensional SOCs.	ITC	2008	DBLP DOI BibTeX RDF
1	Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Hai Helen Li, Yiran Chen	Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.	DAC	2008	DBLP DOI BibTeX RDF	3D stacking, MRAM
1	Feng Wang 0004, Xiaoxia Wu, Yuan Xie	Variability-driven module selection with joint design time optimization and post-silicon tuning.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie	Test-access mechanism optimization for core-based three-dimensional SOCs.	ICCD	2008	DBLP DOI BibTeX RDF
1	Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie	Comparative analysis of NBTI effects on low power and high performance flip-flops.	ICCD	2008	DBLP DOI BibTeX RDF
1	Feng Wang 0004, Michael DeBole, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin	On-chip bus thermal analysis and optimisation.	IET Computers & Digital Techniques	2007	DBLP DOI BibTeX RDF
1	Feng Wang 0004, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan	Variation-aware task allocation and scheduling for MPSoC.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Xiaoxia Wu, Paul Falkenstern, Yuan Xie	Scan chain design for three-dimensional integrated circuits (3D ICs).	ICCD	2007	DBLP DOI BibTeX RDF
1	Wei-Lun Hung, Xiaoxia Wu, Yuan Xie	Guaranteeing performance yield in high-level synthesis.	ICCAD	2006	DBLP DOI BibTeX RDF

Publications of "Xiaoxia Wu" ( http://dblp.L3S.de/Authors/Xiaoxia_Wu )