Search results for "Xijiang Lin"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer	Power Aware Embedded Test.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Elif Alpaslan, Yu Huang 0005, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak	On Reducing Scan Shift Activity at RTL.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab	Low capture power at-speed test in EDT environment.	ITC	2010	DBLP DOI BibTeX RDF
1	Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab	Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains.	ITC	2010	DBLP DOI BibTeX RDF
1	Dat Tran, LeRoy Winemberg, Darrell Carder, Xijiang Lin, Joe LeBritton, Bruce Swanson	Detecting and diagnosing open defects.	ITC	2010	DBLP DOI BibTeX RDF
1	Xijiang Lin, Janusz Rajski	Adaptive Low Shift Power Test Pattern Generator for Logic BIST.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer	Low-Power Scan Operation in Test Compression Environment.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Xijiang Lin, Mark Kassab	Test Generation for Designs with On-Chip Clock Generators.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Xijiang Lin, Yu Huang 0005	Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Scan shift, Low power test, Scan test, Signal probability
1	Xijiang Lin, Janusz Rajski	Test Generation for Interconnect Opens.	ITC	2008	DBLP DOI BibTeX RDF
1	Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer	Low Power Scan Shift and Capture in the EDT Environment.	ITC	2008	DBLP DOI BibTeX RDF
1	Elif Alpaslan, Yu Huang 0005, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak	Reducing Scan Shift Power at RTL.	VTS	2008	DBLP DOI BibTeX RDF	Test Power Reduction, Power-Sensitive Scan Cell, RTL DFT, Timing Closure, Scan Based Test
1	Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press	Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality	CoRR	2007	DBLP BibTeX RDF
1	Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski	Scan-Based Tests with Low Switching Activity.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	scan shift, test response capture, supply current, power dissipation, switching activity, scan-based test
1	Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski	Low Shift and Capture Power Scan Tests.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski	Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs.	ITC	2006	DBLP DOI BibTeX RDF
1	Xijiang Lin, Janusz Rajski	The Impacts of Untestable Defects on Transition Fault Testing.	VTS	2006	DBLP DOI BibTeX RDF
1	Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski	Scan Tests with Multiple Fault Activation Cycles for Delay Faults.	VTS	2006	DBLP DOI BibTeX RDF
1	Xijiang Lin, Janusz Rajski	Propagation delay fault: a new fault model to test delay faults.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Matthias Beck, Olivier Barondeau, Frank Poehl, Xijiang Lin, Ron Press	Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study.	VTS	2005	DBLP DOI BibTeX RDF
1	Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press	Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality.	DATE	2005	DBLP DOI BibTeX RDF
1	Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli	High-Frequency, At-Speed Scan Testing.	IEEE Design & Test of Computers	2003	DBLP DOI BibTeX RDF
1	Xijiang Lin, Rob Thompson	Test generation for designs with multiple clocks.	DAC	2003	DBLP DOI BibTeX RDF	clock domain, ATPG, scan design
1	Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich	Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture.	VTS	2002	DBLP DOI BibTeX RDF	Microprocessor, Delay Testing
1	Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski	Conflict driven techniques for improving deterministic test pattern generation.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy	On static test compaction and test pattern ordering for scan designs.	ITC	2001	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin	Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan. (PDF / PS)	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
1	Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy	SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration.	VTS	2000	DBLP DOI BibTeX RDF	Test Segment, Parallel Pattern Simulator, Vector Restoration, Single Fault Restoration, Fault Coverage, Synchronous Sequential Circuits, Test Length, Static Test Compaction
1	Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin	Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits.	VTS	1999	DBLP DOI BibTeX RDF
1	Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy	Full Scan Fault Coverage With Partial Scan.	DATE	1999	DBLP DOI BibTeX RDF
1	Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy	Techniques for improving the efficiency of sequential circuit test generation.	ICCAD	1999	DBLP BibTeX RDF
1	Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy	On Removing Redundant Faults in Synchronous Sequential Circuits. (PDF / PS)	VTS	1998	DBLP DOI BibTeX RDF
1	Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy	MIX: A Test Generation System for Synchronous Sequential Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF	deterministic test generation genetic optimization based test generation restricted multiple observation time approach state based test generation synchronous sequential circuits

Publications of "Xijiang Lin" ( http://dblp.L3S.de/Authors/Xijiang_Lin )