Search results for "Xilinx FPGA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	George Kiokes, Nikolaos K. Uzunoglu	Development of a simulation Environment for Vehicular communications, implementation of FEC coding chain in Xilinx FPGA based on IEEE 802.11p standard.	WOWMOM	2009	DBLP DOI BibTeX RDF
2	Abderrahim Doumar, Hideo Ito	Testing approach within FPGA-based fault tolerant systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
2	Adam Postula, David Abramson, Paul Logothetis	The Design of a Specialised Processor for the Simulation of Sintering A. Postula.	EUROMICRO	1996	DBLP DOI BibTeX RDF	specialised processor, sintering simulation, metallurgical sintering, commercially available gate array technology, Xilinx FPGA, Aptix FPIC switch technology, FPGAs, Monte-Carlo simulation, special purpose computers
1	Ignacio Bravo, Alfredo Gardel, Beatriz Pérez, José Luis Lázaro, Jorge García, David Salido	A new approach to evaluating internal Xilinx FPGA resources.	Journal of Systems Architecture - Embedded Systems Design	2011	DBLP DOI BibTeX RDF
1	Martin Straka, Jan Kastil, Zdenek Kotásek	SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems.	DSD	2011	DBLP DOI BibTeX RDF
1	Rodrigo Neri de Souza, Daiana Nascimento Muniz, Andre Vaz da Silva Fidalgo	Ethernet communication platform for synthesized devices in Xilinx FPGA.	EUROCON	2011	DBLP DOI BibTeX RDF
1	Mohamed El-Hadedy, Martin Margala, Danilo Gligoroski, Svein J. Knapskog	Resource-efficient implementation of Blue Midnight Wish-256 hash function on Xilinx FPGA platform.	IAS	2010	DBLP DOI BibTeX RDF
1	Cuong Pham-Quoc, Anh-Vu Dinh-Duc	Hazard-free Muller Gates for Implementing Asynchronous Circuits on Xilinx FPGA.	DELTA	2010	DBLP DOI BibTeX RDF
1	Brahim Al Farisi, Karel Bruneel, Harald Devos, Dirk Stroobandt	Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	parameterizable configurations, tmap, fpga, reconfigurable computing, run-time reconfiguration, srl, icap
1	Vincenzo Rana, Donatella Sciuto	A novel design framework for the design of reconfigurable systems based on NoCs.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	network-on-chip, reconfigurable computing, design flow, mapping algorithm
1	Flavius Gruian, Mark Westmijze	Investigating hardware micro-instruction folding in a Java embedded processor.	JTRES	2010	DBLP DOI BibTeX RDF	BlueJEP, bytecode folding, embedded systems, Java processors, Bluespec
1	Rekha K. James, K. Poulose Jacob, Sreela Sasi	Double Digit Decimal Multiplier on XILINX FPGA.	ESA	2009	DBLP BibTeX RDF
1	Ray Bittner	Bus mastering PCI express in an FPGA.	FPGA	2009	DBLP DOI BibTeX RDF	bus mastering, pcie, performance, fpga, design, pci express
1	Barry Schulz, Chirag Parikh, Christian Trefftz	Opportunities for parallelism when implementing algorithms in VHDL - a case study - Shift-Or.	EIT	2009	DBLP DOI BibTeX RDF
1	Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker	FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing.	ARC	2009	DBLP DOI BibTeX RDF	design assurance, bitstream debugging, security, FPGA, Reconfigurable Computing, design verification, EDA tools
1	Hesham Abdel Slam Aly Elzouka	FPGA Based Implementation of Robust Watermarking System.	ITNG	2008	DBLP DOI BibTeX RDF	Electronic Watermarking, Xilinx FPGA, Embedding Systems, Cryptography
1	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	High-throughput interconnect wave-pipelining for global communication in FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF
1	Young H. Cho, William H. Mangione-Smith	Deep network packet filter design for reconfigurable devices.	ACM Trans. Embedded Comput. Syst.	2008	DBLP DOI BibTeX RDF	string filter, Firewall, worm, network intrusion detection, virus
1	Matthew Shelburne, Cameron Patterson, Peter Athanas, Mark Jones, Brian Martin, Ryan Fong	Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip.	FPL	2008	DBLP DOI BibTeX RDF
1	Pradipta Roy, Prabir Kumar Biswas	VLSI Implementation of Fast Connected Component Labeling Using Finite State Machine Based Cell Network.	ICVGIP	2008	DBLP DOI BibTeX RDF
1	Zbigniew Kokosinski, Bartlomiej Malus	FPGA Implementations of a Parallel Associative Processor with Multi-Comparand Multi-Search Operations.	ISPDC	2008	DBLP DOI BibTeX RDF
1	Wenjun Wang, Xiaoguang Wu, Xiaoxuan Zhu, Guixia Kang, Xiaofeng Tao	A 223Mbps FPGA Implementation of (10240, 5120) Irregular Structured Low Density Parity Check Decoder.	VTC Spring	2008	DBLP DOI BibTeX RDF
1	Karthik Baddam, Mark Zwolinski	Divided Backend Duplication Methodology for Balanced Dual Rail Routing.	CHES	2008	DBLP DOI BibTeX RDF	Dual Rail Routing, Dual Rail FPGA Implementation, Differential Power Analysis
1	Reza Ebrahimi Atani, Sattar Mirzakuchaki, Shahabaddin Ebrahimi Atani	Design and Implementation of an Image CoProcessor.	ICISP	2008	DBLP DOI BibTeX RDF
1	Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan	Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA.	MEMOCODE	2007	DBLP DOI BibTeX RDF
1	Martin Straka, Jiri Tobola, Zdenek Kotásek	Checker Design for On-line Testing of Xilinx FPGA Communication Protocols.	DFT	2007	DBLP DOI BibTeX RDF
1	David Arditti, Côme Berbain, Olivier Billet, Henri Gilbert	Compact FPGA implementations of QUAD.	ASIACCS	2007	DBLP DOI BibTeX RDF
1	Flavius Gruian, Mark Westmijze	BlueJEP: a flexible and high-performance Java embedded processor.	JTRES	2007	DBLP DOI BibTeX RDF	embedded systems, Java processor, Bluespec
1	Camel Tanougast, Serge Weber, Gilles Millerioux, Ahmed Bouridane, Jamal Daafouz	An Fpga implementation of the HME self-synchronizing stream cipher for Enhanced security and performance.	AHS	2007	DBLP DOI BibTeX RDF
1	Weidong Kuang, Casto Manuel Ibarra, Peiyi Zhao	Soft Error Hardening for Asynchronous Circuits.	DFT	2007	DBLP DOI BibTeX RDF
1	Cédric Lauradoux	From Hardware to Software Synthesis of Linear Feedback Shift Registers.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Muhammad Bilal, Shahid Masud	Efficient Color Space Conversion using Custom Instruction in a RISC Processor.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Wen-Chung Kao, Hong-Shuo Tai, Chia-Ping Shen, Jia-An Ye, Hong-Fa Ho	A Pipelined Architecture Design for Trilateral Noise Filtering.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Himanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick Wolf	Design Methodology and CAD Tools for Prototyping Delta-Sigma Fractional-N Frequency Synthesizers.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
1	Vagner S. Rosa, Wagston T. Staehler, Arnaldo Azevedo, Bruno Zatt, Roger Endrigo Carvalho Porto, Luciano Volcan Agostini, Sergio Bampi, Altamiro Amadeu Susin	FPGA Prototyping Strategy for a H.264/AVC Video Decoder.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
1	Flavius Gruian, Mark Westmijze	BluEJAMM: A Bluespec Embedded Java Architecture with Memory Management.	SYNASC	2007	DBLP DOI BibTeX RDF
1	Parimal Patel	Tutorial IND2A: Embedded Systems Design with Xilinx Virtex-5 Series FPGA.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	S. Himavathi, D. Anitha, A. Muthuramalingam	Feedforward Neural Network Implementation in FPGA Using Layer Multiplexing for Effective Resource Utilization.	IEEE Transactions on Neural Networks	2007	DBLP DOI BibTeX RDF
1	Thinh Ngoc Tran, Surin Kittitornkun	FPGA-Based Cuckoo Hashing for Pattern Matching in NIDS/NIPS.	APNOMS	2007	DBLP DOI BibTeX RDF	NIPS, FPGA, Pattern Matching, NIDS, Cuckoo Hashing
1	Jin-Oh Jeon, Su-Bong Ryu, Sang-Jo Park, Min-Sup Kang	Strong Authentication Protocol for RFID Tag Using SHA-1 Hash Algorithm.	ICCSA	2007	DBLP DOI BibTeX RDF	Strong authentication protocol, SHA-1 hash algorithm, Three-way challenge response, ISO/IEC 1800-3 standard, Digital Codec design, RFID Tag
1	Tian Song, Zhizhong Tang, Dongsheng Wang	Multilevel Pattern Matching Architecture for Network Intrusion Detection and Prevention System.	ICESS	2007	DBLP DOI BibTeX RDF
1	Roman C. Kordasiewicz, Shahram Shirani	On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	JVT, integer DCT, Xilinx Virtex 2-Pro, PPC, FPGA, architecture, H.264/AVC, Quantization, hardware implementations, MPEG4
1	Roman C. Kordasiewicz, Shahram Shirani	On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	JVT, integer DCT, Xilinx Virtex 2-Pro, PPC, FPGA, architecture, H.264/AVC, quantization, hardware implementations, MPEG4
1	H. Shrikumar	40Gbps de-layered silicon protocol engine for TCP record.	DATE	2006	DBLP DOI BibTeX RDF
1	David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen	Application-specific customization of parameterized FPGA soft-core processors.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Kyrre Glette, Jim Torresen, Moritoshi Yasunaga, Yoshiki Yamaguchi	On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition.	AHS	2006	DBLP DOI BibTeX RDF
1	Seonyoung Lee, Kyeongsoon Cho	Implementation of an AMBA-Compliant IP for H.264 Transform and Quantization.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Marjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro	Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation.	ASAP	2006	DBLP DOI BibTeX RDF
1	Hongtu Jiang, Viktor Öwall, Håkan Ardö	Real-Time Video Segmentation with VGA Resolution and Memory Bandwidth Reduction.	AVSS	2006	DBLP DOI BibTeX RDF
1	Pavel Kubalík, Radek Dobias, Hana Kubatova	Dependable Design for FPGA Based on Duplex System and Reconfiguration.	DSD	2006	DBLP DOI BibTeX RDF
1	Luciano Volcan Agostini, Arnaldo Azevedo, Vagner S. Rosa, Eduardo A. Berriel, Tatiana Gadelha Serra dos Santos, Sergio Bampi, Altamiro Amadeu Susin	FPGA Design of A H.264/AVC Main Profile Decoder for HDTV.	FPL	2006	DBLP DOI BibTeX RDF
1	R. P. Jacobi, R. B. Cardoso, Geovany Araujo Borges	VoC: a reconfigurable matrix for stereo vision processing.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Christopher Kachris, Stamatis Vassiliadis	Analysis of a reconfigurable network processor.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Junho Cho, Hoseok Chang, Wonyong Sung	An FPGA based SIMD processor with a vector memory unit.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Seyed E. Esmaeili, Nabil I. Khachab, Moustafa Y. Ghannam	Effect of Glitches on the Efficiency of Components' Region-Constrained Placement as a Fast Approach to Reduce FPGA's Dynamic Power Consumption.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Lin Qiang, Nigel M. Allinson	Spatial Optical Distortion Correction in an FPGA.	SiPS	2006	DBLP DOI BibTeX RDF
1	Lin Qiang, Nigel M. Allinson	FPGA Implementation of Pipelined Architecture for Optical Imaging Distortion Correction.	SiPS	2006	DBLP DOI BibTeX RDF
1	J. Bhattacharyya, P. Mandal, R. Banerjee, Swapna Banerjee	Real Time Dynamic Receive Apodization for an Ultrasound Imaging System.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Dae Y. Kim, Sunil Kim, Lynn Choi, Hyogon Kim	A High-Throughput System Architecture for Deep Packet Filtering in Network Intrusion Prevention.	ARCS	2006	DBLP DOI BibTeX RDF
1	Sven Beyer, Christian Jacobi 0002, Daniel Kröning, Dirk Leinenbach, Wolfgang J. Paul	Putting it all together - Formal verification of the VAMP.	STTT	2006	DBLP DOI BibTeX RDF	Complete microprocessor verification, Tomasulo scheduler, Cache memory interface, Model checking, Formal methods, Theorem proving, Floating point unit
1	Athanasios Kakarountas, Haralambos Michail, Athanasios Milidonis, Costas E. Goutis, George Theodoridis	High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications.	The Journal of Supercomputing	2006	DBLP DOI BibTeX RDF	high-speed performance, Security, FPGA, hash function, hardware implementation
1	V. Jaiganesh, Murugan Sankaradass	PC based heart rate monitor implemented in XILINX FPGA and analysing the heart rate.	Circuits, Signals, and Systems	2005	DBLP BibTeX RDF
1	Lei Yang, Manyuan Shen, Hui Liu, C.-J. Richard Shi	An FPGA implementation of low-density parity-check code decoder with multi-rate capability.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Gang Quan, James P. Davis, Siddhaveerasharan Devarkal, Duncan A. Buell	High-level synthesis for large bit-width multipliers on FPGAs: a case study.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	FPGA devices, large-scale integer multipliers, high level synthesis, reconfigurable computing, design exploration
1	Michael Attig, John W. Lockwood	A framework for rule processing in reconfigurable network systems (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
1	Haoyu Song, John W. Lockwood	Efficient packet classification for network intrusion detection using FPGA.	FPGA	2005	DBLP DOI BibTeX RDF	BV, tree bitmap, FPGA, reconfigurable hardware, packet classification, TCAM, NIDS
1	Bo Yang, Nikhil Joshi, Ramesh Karri	A constant array multiplier core generator with dynamic partial evaluation architecture selection (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
1	Miguel Morales-Sandoval, Claudia Feregrino Uribe	A Hardware Architecture for Elliptic Curve Cryptography and Lossless Data Compression.	CONIELECOMP	2005	DBLP DOI BibTeX RDF
1	Bita Gorjiara, Daniel D. Gajski	Custom Processor Design Using NISC: A Case-Study on DCT algorithm.	ESTImedia	2005	DBLP DOI BibTeX RDF
1	Michael Attig, John W. Lockwood	A Framework for Rule Processing in Reconfigurable Network Systems.	FCCM	2005	DBLP DOI BibTeX RDF
1	Yeong-Kang Lai, Chih-Chung Chou, Yu-Chieh Chung	A simple and cost effective video encoder with memory-reducing CAVLC.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Wei Wang 0003, Xiaolin Zhang, Chenyang Yang, M. N. S. Swamy, M. Omair Ahmad	RRNS Quasi-Chaotic Coding and Its FPGA Implementation.	SNPD	2005	DBLP DOI BibTeX RDF
1	Chunhui Zhang, Yun Long, Fadi J. Kurdahi	A Scalable Embedded JPEG2000 Architecture.	SAMOS	2005	DBLP DOI BibTeX RDF
1	Bo Yang, Ramesh Karri, David A. McGrew	Divide and concatenate: a scalable hardware architecture for universal MAC.	FPGA	2004	DBLP DOI BibTeX RDF
1	Soheil Ghiasi, Elaheh Bozorgzadeh, Siddharth Choudhuri, Majid Sarrafzadeh	A unified theory of timing budget management.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Refik Sever, A. Neslin Ismailoglu, Yusuf Çagatay Tekmen, Murat Askar, Burak Okcan	A High Speed FPGA Implementation of the Rijndael Algorithm.	DSD	2004	DBLP DOI BibTeX RDF
1	Ganesh K. Venayagamoorthy, Venu G. Gudise	Swarm Intelligence for Digital Circuits Implementation on Field Programmable Gate Arrays Platforms.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
1	Venu G. Gudise, Ganesh K. Venayagamoorthy	FPGA Placement and Routing Using Particle Swarm Optimization.	ISVLSI	2004	DBLP DOI BibTeX RDF
1	André Meisel, Markus Visarius, Wolfram Hardt, Stefan Ihmor	Self-Reconfiguration of Communication Interfaces.	IEEE International Workshop on Rapid System Prototyping	2004	DBLP DOI BibTeX RDF
1	Manvendra Singh, B. S. Chauhan, N. K. Sharma	VLSI Architecture of Centroid Tracking Algorithms for Video Tracker.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Renuka Kumara C., Sridhara Nayak	FPGA Based Implementation of an Invisible-Robust Image Watermarking Encoder.	CIT	2004	DBLP DOI BibTeX RDF
1	Michael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen Becker	Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems.	FPL	2004	DBLP DOI BibTeX RDF
1	Zexin Pan, Srikanth Venkateswaran, Swathi Tanjore Gurumani, B. Earl Wells	Exploiting Fine-Grain Parallelism of IDEA Using Xilinx FPGA.	ISCA PDCS	2003	DBLP BibTeX RDF
1	Tan Yiyu, Zhang Ning	An Image Processing System Scheme in B Mode Ultrasonic Ophthalmological Scanner.	CBMS	2003	DBLP DOI BibTeX RDF
1	Cecilia Metra, Stefano Di Francescantonio, Martin Omaña	Automatic Modification of Sequential Circuits for Self-Checking Implementation.	DFT	2003	DBLP DOI BibTeX RDF
1	Michael A. Soderstrand	CSD multipliers for FPGA DSP applications.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann, Christophe Bobda	A New Approach of a Self-Timed Bit-Serial Synchronous Pipeline Architecture.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
1	Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann, Ulrich Dierkes, Carsten Rustemeier	Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline Architecture.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Bipul Das, Swapna Banerjee	A Memory Efficient 3-D DWT Architecture.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Seda Ogrenci Memik, Aggelos K. Katsaggelos, Majid Sarrafzadeh	Analysis and FPGA Implementation of Image Restoration under Resource Constraints.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	FPGA, image segmentation, image restoration
1	Sven Beyer, Christian Jacobi 0002, Daniel Kroening, Dirk Leinenbach, Wolfgang J. Paul	Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP.	CHARME	2003	DBLP DOI BibTeX RDF
1	T. Sansaloni, Javier Valls, Keshab K. Parhi	Digit-Serial Complex-Number Multipliers on FPGAs.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	complex-number multipliers, digit-serial arithmetic, FPGA, Booth recoding
1	N. Sudha	Design of a Cellular Architecture for Fast Computation of the Skeleton.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	cellular architecture, VLSI, skeleton, binary image
1	Anup Kumar Raghavan, Peter Sutton	JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs. (PDF / PS)	IPDPS	2002	DBLP DOI BibTeX RDF	JBits, FPGA design flow, Partial Bitstream, Xilinx Virtex, Partial Reconfiguration
1	Urs Kanus, Gregor Wetekam, Johannes Hirche, Michael Meißner	VIZARD II: An FPGA-based Interactive Volume Rendering System.	FPL	2002	DBLP DOI BibTeX RDF
1	Peter McCurry, Fearghal Morgan, Liam Kilmartin	Xilinx FPGA implementation of an image classifier for object detection applications.	ICIP	2001	DBLP DOI BibTeX RDF
1	Andrzej Ryszko, Kazimierz Wiatr	An Assesment of FPGA Suitability for Implementation of Real-Time Motion Estimation.	DSD	2001	DBLP DOI BibTeX RDF
1	Abbes Amira, Ahmed Bouridane, Peter Milligan	An FPGA based Walsh Hadamard transforms.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Viktor Fischer, Milos Drutarovský	Two Methods of Rijndael Implementation in Reconfigurable Hardware.	CHES	2001	DBLP DOI BibTeX RDF
1	Tsutomu Maruyama, Yoshiki Yamaguchi, Atsushi Kawase	An Approach to Real-Time Visualization of PIV Method with FPGA.	FPL	2001	DBLP DOI BibTeX RDF