Search results for "Yale N. Patt"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt	Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multicore Memory Systems.	ACM Trans. Comput. Syst.	2012	DBLP DOI BibTeX RDF
1	José A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt	Bottleneck identification and scheduling in multithreaded applications.	ASPLOS	2012	DBLP DOI BibTeX RDF
1	M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt	Data Marshaling for Multicore Systems.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Yale N. Patt, Onur Mutlu	Top Picks [Guest editors' introduction].	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt	Prefetch-Aware Memory Controllers.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	prefetching, DRAM, Memory systems, memory controllers, multi-core systems
1	Yale N. Patt	HPS Microarchitecture.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
1	Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt	Prefetch-aware shared resource management for multi-core systems.	ISCA	2011	DBLP DOI BibTeX RDF
1	Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt	Improving GPU performance via large warps and two-level warp scheduling.	MICRO	2011	DBLP DOI BibTeX RDF
1	Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, José A. Joao, Onur Mutlu, Yale N. Patt	Parallel application memory scheduling.	MICRO	2011	DBLP DOI BibTeX RDF
1	M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt	Accelerating Critical Section Execution with Asymmetric Multicore Architectures.	IEEE Micro	2010	DBLP DOI BibTeX RDF	heterogeneous cores, parallel programming, CMP, multicore, locks, critical sections, serialization
1	M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt	Data marshaling for multi-core architectures.	ISCA	2010	DBLP DOI BibTeX RDF	staged execution, pipelining, cmp, critical sections
1	M. Aater Suleman, Moinuddin K. Qureshi, Khubaib, Yale N. Patt	Feedback-directed pipeline parallelism.	PACT	2010	DBLP DOI BibTeX RDF
1	Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt	Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems.	ASPLOS	2010	DBLP DOI BibTeX RDF	fairness, shared memory systems, system performance, multi-core systems
1	Yale N. Patt, Pierfrancesco Foglia, Evelyn Duesterwald, Paolo Faraboschi, Xavier Martorell (eds.)	High Performance Embedded Architectures and Compilers, 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings	HiPEAC	2010	DBLP DOI BibTeX RDF
1	Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn	Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Yale N. Patt	What Else Is Broken? Can We Fix It?	SAMOS	2009	DBLP DOI BibTeX RDF
1	José A. Joao, Onur Mutlu, Yale N. Patt	Flexible reference-counting-based hardware acceleration for garbage collection.	ISCA	2009	DBLP DOI BibTeX RDF	garbage collection, reference counting
1	Yale N. Patt	The Challenges of Multicore: Information and Mis-Information.	ARCS	2009	DBLP DOI BibTeX RDF
1	M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt	Accelerating critical section execution with asymmetric multi-core architectures.	ASPLOS	2009	DBLP DOI BibTeX RDF	heterogeneous cores, parallel programming, cmp, multi-core, locks, critical sections
1	Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt	Coordinated control of multiple prefetchers in multi-core systems.	MICRO	2009	DBLP DOI BibTeX RDF	prefetching, multi-core, feedback control, memory systems
1	Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt	Improving memory bank-level parallelism in the presence of prefetching.	MICRO	2009	DBLP DOI BibTeX RDF
1	Yale N. Patt	Multi-core demands multi-interfaces.	HPCA	2009	DBLP DOI BibTeX RDF
1	Eiman Ebrahimi, Onur Mutlu, Yale N. Patt	Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems.	HPCA	2009	DBLP DOI BibTeX RDF
1	Yale N. Patt	Multi-core demands multi-interfaces.	PPOPP	2009	DBLP DOI BibTeX RDF	performance, design, multicore, software interface
1	Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer	Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching.	IEEE Micro	2008	DBLP DOI BibTeX RDF	thrashing, set sampling, set dueling, cache, insertion, replacement
1	Yale N. Patt	Can They Be Fixed: Some Thoughts After 40 Years in the Business.	SAMOS	2008	DBLP DOI BibTeX RDF
1	Francis Tseng, Yale N. Patt	Achieving Out-of-Order Performance with Almost In-Order Complexity.	ISCA	2008	DBLP DOI BibTeX RDF
1	M. Aater Suleman, Moinuddin K. Qureshi, Yale N. Patt	Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs.	ASPLOS	2008	DBLP DOI BibTeX RDF	synchronization, CMP, bandwidth, multi-threaded
1	José A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, Yale N. Patt	Improving the performance of object-oriented languages with dynamic predication of indirect jumps.	ASPLOS	2008	DBLP DOI BibTeX RDF	dynamic predication, indirect jumps, object-oriented languages, predicated execution, virtual functions
1	Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt	Prefetch-Aware DRAM Controllers.	MICRO	2008	DBLP DOI BibTeX RDF
1	Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt	Performance-aware speculation control using wrong path usefulness prediction.	HPCA	2008	DBLP DOI BibTeX RDF
1	José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt	Dynamic Predication of Indirect Jumps.	Computer Architecture Letters	2007	DBLP DOI BibTeX RDF
1	José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt	Dynamic Predication of Indirect Jumps.	Computer Architecture Letters	2007	DBLP DOI BibTeX RDF
1	Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt	Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication.	IEEE Micro	2007	DBLP DOI BibTeX RDF	dynamic predication, adaptivity, energy efficiency, pipelining, instruction level parallelism, branch prediction, predication
1	Joel S. Emer, Mark D. Hill, Yale N. Patt, Joshua J. Yi, Derek Chiou, Resit Sendag	Single-Threaded vs. Multithreaded: Where Should We Focus?	IEEE Micro	2007	DBLP DOI BibTeX RDF	multiple data stream architectures (multiprocessors), microarchitecture implementation considerations, processor architectures, computer systems organization, single data stream architectures
1	Yale N. Patt	The Transformation Hierarchy in the Era of Multi-core.	HiPC	2007	DBLP DOI BibTeX RDF
1	Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer	Adaptive insertion policies for high performance caching.	ISCA	2007	DBLP DOI BibTeX RDF	set dueling, set sampling, thrashing, replacement
1	Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn	VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization.	ISCA	2007	DBLP DOI BibTeX RDF	devirtualization, indirect branch prediction, virtual functions
1	Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt	Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors.	CGO	2007	DBLP DOI BibTeX RDF
1	Santhosh Srinath, Onur Mutlu, Hyesoon Kim, Yale N. Patt	Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers.	HPCA	2007	DBLP DOI BibTeX RDF
1	Moinuddin K. Qureshi, M. Aater Suleman, Yale N. Patt	Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines.	HPCA	2007	DBLP DOI BibTeX RDF
1	Jean-Luc Gaudiot, Yale N. Patt, Kevin Skadron	Foreword.	Computer Architecture Letters	2006	DBLP DOI BibTeX RDF
1	Onur Mutlu, Hyesoon Kim, Yale N. Patt	Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance.	IEEE Micro	2006	DBLP DOI BibTeX RDF	memory latency tolerance, processors, Runahead execution
1	Hyesoon Kim, Onur Mutlu, Yale N. Patt, Jared Stark	Wish Branches: Enabling Adaptive and Aggressive Predicated Execution.	IEEE Micro	2006	DBLP DOI BibTeX RDF	Wish branches, wish loops, branch prediction, predicated execution
1	Onur Mutlu, Hyesoon Kim, Yale N. Patt	Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	value prediction, memory-level parallelism, runahead execution, Single data stream architectures
1	Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt	A Case for MLP-Aware Cache Replacement.	ISCA	2006	DBLP DOI BibTeX RDF
1	Yale N. Patt	Computer Architecture Research and Future Microprocessors: Where Do We Go from Here?	ISCA	2006	DBLP DOI BibTeX RDF
1	Hyesoon Kim, M. Aater Suleman, Onur Mutlu, Yale N. Patt	2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set.	CGO	2006	DBLP DOI BibTeX RDF
1	Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt	Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths.	MICRO	2006	DBLP DOI BibTeX RDF
1	Moinuddin K. Qureshi, Yale N. Patt	Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches.	MICRO	2006	DBLP DOI BibTeX RDF
1	Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt	Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References.	International Journal of Parallel Programming	2005	DBLP DOI BibTeX RDF	cache filtering, speculative memory references, Caches, runahead execution, cache pollution
1	Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt	On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor.	Computer Architecture Letters	2005	DBLP DOI BibTeX RDF
1	Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt	An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	processor performance modeling, speculative execution, runahead execution, Single data stream architectures
1	Onur Mutlu, Hyesoon Kim, Yale N. Patt	Techniques for Efficient Processing in Runahead Execution Engines.	ISCA	2005	DBLP DOI BibTeX RDF
1	Moinuddin K. Qureshi, David Thompson, Yale N. Patt	The V-Way Cache: Demand Based Associativity via Global Replacement.	ISCA	2005	DBLP DOI BibTeX RDF
1	Yale N. Patt	A Unifying Theory of Distributed Processing (Or, The Chutzpah One Should Expect When You Invite a Microarchitect into Your Sandbox). (PDF / PS)	IPDPS	2005	DBLP DOI BibTeX RDF
1	Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt	Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors.	DSN	2005	DBLP DOI BibTeX RDF
1	Onur Mutlu, Hyesoon Kim, Yale N. Patt	Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns.	MICRO	2005	DBLP DOI BibTeX RDF
1	Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt	Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution.	MICRO	2005	DBLP DOI BibTeX RDF
1	Yale N. Patt	The microprocessor of the year 2014: do Pentium 4, Pentium M, and Power 5 provide any hints?	AICCSA	2005	DBLP DOI BibTeX RDF
1	Yale N. Patt, Sanjay J. Patel	Introduction to computing systems - from bits and gates to C and beyond (2. ed.).		2004	RDF
1	Brad Calder, Daniel Citron, Yale N. Patt, James E. Smith	The future of simulation: A field of dreams.	ISPASS	2004	DBLP DOI BibTeX RDF
1	Yale N. Patt	Opening and keynote 1.	ISPASS	2004	DBLP DOI BibTeX RDF
1	David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt	Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery.	MICRO	2004	DBLP DOI BibTeX RDF
1	Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt	Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance.	SBAC-PAD	2004	DBLP DOI BibTeX RDF
1	Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt	Understanding the effects of wrong-path memory references on processor performance.	WMPI	2004	DBLP DOI BibTeX RDF	processor performance analysis, wrong path modeling, wrong-path memory references, speculative execution, data prefetching, execution-driven simulation, cache pollution
1	Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt	Runahead Execution: An Effective Alternative to Large Instruction Windows.	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Yale N. Patt	The High Performance Microprocessor in the Year 2013: What Will It Look Like? What It Won't Look Like?	HiPC	2003	DBLP DOI BibTeX RDF
1	Paul Racunas, Yale N. Patt	Partitioned first-level cache design for clustered microarchitectures.	ICS	2003	DBLP DOI BibTeX RDF	partitioned cache, clustered microarchitecture
1	Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt	Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors.	HPCA	2003	DBLP DOI BibTeX RDF
1	Yale N. Patt, Dirk Grunwald, Kevin Skadron (eds.)	29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA	ISCA	2002	DBLP BibTeX RDF
1	Robert S. Chappell, Francis Tseng, Yale N. Patt, Adi Yoaz	Difficult-Path Branch Prediction Using Subordinate Microthreads. (PDF / PS)	ISCA	2002	DBLP DOI BibTeX RDF	high performance microprocessor, SSMT, microthread, branch prediction, microarchitecture, SMT, helper thread
1	Robert S. Chappell, Francis Tseng, Adi Yoaz, Yale N. Patt	Microarchitectural support for precomputation microthreads.	MICRO	2002	DBLP DOI BibTeX RDF
1	Stephen W. Melvin, Yale N. Patt	Handling of packet dependencies: a critical issue for highly parallel network processors.	CASES	2002	DBLP DOI BibTeX RDF	memory synchronization, packet dependencies, parallel processing, network processors, processor architecture, thread level speculation, multithreaded processors, packet processing
1	Mary D. Brown, Yale N. Patt	Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files.	HPCA	2002	DBLP DOI BibTeX RDF	redundant binary, limited bypass, pipelined register file, signed digit
1	Mary D. Brown, Jared Stark, Yale N. Patt	Select-free instruction scheduling logic.	MICRO	2001	DBLP DOI BibTeX RDF
1	Judith L. Gersting, Peter B. Henderson, Philip Machanick, Yale N. Patt	Programming early considered harmful.	SIGCSE	2001	DBLP DOI BibTeX RDF
1	Gregory R. Ganger, Marshall K. McKusick, Craig A. N. Soules, Yale N. Patt	Soft updates: a solution to the metadata update problem in file systems.	ACM Trans. Comput. Syst.	2000	DBLP DOI BibTeX RDF
1	Jared Stark, Mary D. Brown, Yale N. Patt	On pipelining dynamic instruction scheduling logic.	MICRO	2000	DBLP DOI BibTeX RDF
1	Yale N. Patt	Higher and Higher Performance Microprocessors: Are The Problems Just Too Hard To Solve? (PDF / PS)	EUROMICRO	2000	DBLP DOI BibTeX RDF
1	Sanjay J. Patel, Daniel H. Friendly, Yale N. Patt	Evaluation of Design Options for the Trace Cache Fetch Mechanism.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	High bandwidth fetch mechanisms, wide issue machines, speculative execution, instruction cache, trace cache
1	Robert S. Chappell, Jared Stark, Sangwook P. Kim, Steven K. Reinhardt, Yale N. Patt	Simultaneous Subordinate Microthreading (SSMT).	ISCA	1999	DBLP DOI BibTeX RDF
1	Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt	Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures.	International Journal of Parallel Programming	1998	DBLP DOI BibTeX RDF
1	Gregory R. Ganger, Yale N. Patt	Using System-Level Models to Evaluate I/O Subsystem Designs.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	storage subsystem, disk system, disk modeling, simulation, performance model, disk scheduling, system-level model, system simulation, I/O subsystems
1	Wen-mei W. Hwu, Yale N. Patt	HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
1	Wen-mei W. Hwu, Yale N. Patt	Retrospective: HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
1	Tse-Yu Yeh, Yale N. Patt	Alternative Implementations of Two-Level Adaptive Branch Prediction.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
1	Tse-Yu Yeh, Yale N. Patt	Retrospective: Alternative Implementations of Two-Level Adaptive Training Branch Prediction.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
1	Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt	An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work.	ISCA	1998	DBLP DOI BibTeX RDF
1	Sanjay J. Patel, Marius Evers, Yale N. Patt	Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing.	ISCA	1998	DBLP DOI BibTeX RDF
1	Jared Stark, Marius Evers, Yale N. Patt	Variable Length Path Branch Prediction.	ASPLOS	1998	DBLP DOI BibTeX RDF
1	Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt	Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors.	MICRO	1998	DBLP BibTeX RDF
1	Stéphan Jourdan, Jared Stark, Tse-Hao Hsing, Yale N. Patt	Recovery requirements of branch prediction storage structures in the presence of mispredicted-path execution.	International Journal of Parallel Programming	1997	DBLP DOI BibTeX RDF
1	Po-Yung Chang, Marius Evers, Yale N. Patt	Improving branch prediction accuracy by reducing pattern history table interference.	International Journal of Parallel Programming	1997	DBLP DOI BibTeX RDF
1	Yale N. Patt	Identifiying Obstacles in the Path to More.	IEEE Computer	1997	DBLP DOI BibTeX RDF
1	Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, Jared Stark	One Billion Transistors, One Uniprocessor, One Chip.	IEEE Computer	1997	DBLP DOI BibTeX RDF
1	Po-Yung Chang, Eric Hao, Yale N. Patt	Target Prediction for Indirect Jumps.	ISCA	1997	DBLP DOI BibTeX RDF
1	Eric Sprangle, Robert S. Chappell, Mitch Alsup, Yale N. Patt	The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference.	ISCA	1997	DBLP DOI BibTeX RDF	two-level branch prediction, branch prediction, speculative execution, superscalar
1	Jared Stark, Paul Racunas, Yale N. Patt	Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order.	MICRO	1997	DBLP BibTeX RDF	instruction supply, superscalar processors, out-of-order execution
1	Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt	Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism.	MICRO	1997	DBLP BibTeX RDF	high bandwidth fetch mechanisms, wide issue machines, inactive issue, speculative execution, trace cache, partial matching

Publications of "Yale N. Patt" ( http://dblp.L3S.de/Authors/Yale_N._Patt )