Search results for "Yannick Bonhomme"

Found 16 publication records. Showing 16 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Valentin Gherman, Samuel Evain, Fabrice Auzanneau, Yannick Bonhomme	Programmable extended SEC-DED codes for memory errors.	VTS	2011	DBLP DOI BibTeX RDF
1	Valentin Gherman, J. Massas, Samuel Evain, Stéphane Chevobbe, Yannick Bonhomme	Error prediction based on concurrent self-test and reduced slack time.	DATE	2011	DBLP DOI BibTeX RDF
1	Valentin Gherman, Samuel Evain, Nathaniel Seymour, Yannick Bonhomme	Generalized parity-check matrices for SEC-DED codes with fixed parity.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Samuel Evain, Yannick Bonhomme, Valentin Gherman	Programmable restricted SEC codes to mask permanent faults in semiconductor memories.	IOLTS	2010	DBLP DOI BibTeX RDF
1	Richard Buchmann, Mickael Cartron, Yannick Bonhomme	Transaction-based modeling for large scale simulations of heterogeneous systems.	SimuTools	2009	DBLP DOI BibTeX RDF	simulation, modeling
1	Valentin Gherman, Samuel Evain, Mickael Cartron, Nathaniel Seymour, Yannick Bonhomme	System-level hardware-based protection of memories against soft-errors.	DATE	2009	DBLP BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Gated Clock Scheme for Low Power Testing of Logic Cores.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	test-per-scan, test-per-clock, low power design, low power test
1	Patrick Girard, Yannick Bonhomme	Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing.	J. Low Power Electronics	2005	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	Power-Driven Routing-Constrained Scan Chain Design.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	scan chain design, DfT, low power testing, scan testing
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Design of Routing-Constrained Low Power Scan Chains.	DELTA	2004	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Design of Routing-Constrained Low Power Scan Chains.	DATE	2004	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.	ITC	2003	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	Power Driven Chaining of Flip-Flops in Scan Architectures.	ITC	2002	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	Test Power: a Big Issue in Large SOC Designs.	DELTA	2002	DBLP DOI BibTeX RDF	DfT, BIST, Scan, Low Power Testing, Test Power
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Gated Clock Scheme for Low Power Scan-Based BIST.	IOLTW	2001	DBLP DOI BibTeX RDF

Publications of "Yannick Bonhomme" ( http://dblp.L3S.de/Authors/Yannick_Bonhomme )