| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Joseph S. Friedman, Nikhil Rangaraju, Yehea I. Ismail, Bruce W. Wessels |
InMnAs magnetoresistive spin-diode logic.  |
ACM Great Lakes Symposium on VLSI  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kian Haghdad, Mohab Anis, Yehea I. Ismail |
Floorplanning for low power IC design considering temperature variations. |
Microelectronics Journal |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmed Shebaita, Debasish Das, Dusan Petranovic, Yehea I. Ismail |
A Novel Moment Based Framework for Accurate and Efficient Static Timing Analysis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yehea I. Ismail |
Editorial. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack |
FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Khaled Salah, Hani Ragai, Yehea I. Ismail, Alaa El Rouby |
Equivalent lumped element models for various n-port Through Silicon Vias networks. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sally Safwat, Ezz El-Din O. Hussein, Maged Ghoneima, Yehea I. Ismail |
A 12Gbps all digital low power SerDes transceiver for on-chip networking. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Loai G. Salem, Yehea I. Ismail |
Fast hysteretic control of on-chip multi-phase switched-capacitor dc-dc converters. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mina Raymond, Maged Ghoneima, Yehea I. Ismail |
A dynamic calibration scheme for on-chip process and temperature variations. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Khaled Salah, Alaa El Rouby, Hani Ragai, Karim Amin, Yehea I. Ismail |
Compact lumped element model for TSV in 3D-ICs. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Song Liu, Seda Ogrenci Memik, Yehea I. Ismail |
A Comprehensive Tapered buffer optimization algorithm for unified design metrics. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea I. Ismail |
SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced Delay Variation. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ezz El-Din O. Hussein, Yehea I. Ismail |
A novel variation insensitive clock distribution methodology. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | DiaaEldin Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek De |
SRAM dynamic stability estimation using MPFP and its applications. |
Microelectronics Journal |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | DiaaEldin Khalil, Debjit Sinha, Hai Zhou, Yehea I. Ismail |
A Timing-Dependent Power Estimation Framework Considering Coupling. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De |
SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Shizhong Mei, Yehea I. Ismail |
Stable Parallelizable Model Order Reduction for Circuits With Frequency-Dependent Elements. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De |
Serial-Link Bus: A Low-Power On-Chip Bus Architecture. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ja Chun Ku, Yehea I. Ismail |
Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | D. E. Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, Vivek K. De |
Accurate Estimation of SRAM Dynamic Stability. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Maged Ghoneima, Muhammad M. Khellah, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail, Vivek K. De |
Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmed Shebaita, Yehea I. Ismail |
Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | DiaaEldin Khalil, Yehea I. Ismail, Muhammad M. Khellah, Tanay Karnik, Vivek De |
Analytical Model for the Propagation Delay of Through Silicon Vias. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
3D integrated circuits, propagation delay model, dimensional analysis, TSV |
| 1 | DiaaEldin Khalil, Yehea I. Ismail |
A global interconnect link design for many-core microprocessors. |
IFMT |
2008 |
DBLP DOI BibTeX RDF |
interconnect, link, bus, repeater insertion |
| 1 | Yehea I. Ismail |
Interconnect design and limitations in nanoscale technologies. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sami Kirolos, Yehia Massoud, Yehea I. Ismail |
Accurate analytical delay modeling of CMOS clock buffers considering power supply variations. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sami Kirolos, Yehia Massoud, Yehea I. Ismail |
Power-supply-variation-aware timing analysis of synchronous systems. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek K. De |
Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Shizhong Mei, Yehea I. Ismail |
An Accurate Low-Iteration Algorithm for Effective Capacitance Computation. |
Journal of Circuits, Systems, and Computers |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ja Chun Ku, Yehea I. Ismail |
On the Scaling of Temperature-Dependent Effects. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail |
Thermal Management of On-Chip Caches Through Power Density Minimization. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ja Chun Ku, Yehea I. Ismail |
Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Serkan Ozdemir, Arindam Mallik, Ja Chun Ku, Gokhan Memik, Yehea I. Ismail |
Variable latency caches for nanoscale processor. |
SC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ismail |
Modeling and Characterizing Power Variability in Multicore Architectures. |
ISPASS |
2007 |
DBLP DOI BibTeX RDF |
mal-fabricated chip, VariPower, project power variability, microarchitectural block, power variability characterization, statistical analysis, multicore processor, multicore architecture, technology scaling, parameter variation, SPICE simulation |
| 1 | Ja Chun Ku, Yehea I. Ismail |
Thermal-aware methodology for repeater insertion in low-power VLSI circuits. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
low-power design, repeater insertion, temperature-aware design |
| 1 | Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou, Kip Killpack |
NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
modeling, crosstalk, static timing analysis |
| 1 | Ja Chun Ku, Yehea I. Ismail |
A Compact and Accurate Temperature-Dependent Model for CMOS Circuit Delay. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | DiaaEldin Khalil, Yehea I. Ismail |
Approximate Frequency Response Models for RLC Power Grids. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ja Chun Ku, Yehea I. Ismail |
Attaining Thermal Integrity in Nanometer Chips. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmed Shebaita, Yehea I. Ismail |
Variable Threshold Voltage Design Scheme for CMOS Tapered Buffers. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Frank Huebbers, Ali Dasdan, Yehea I. Ismail |
Multi-layer interconnect performance corners for variation-aware timing analysis. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea I. Ismail |
A self-adjusting clock tree architecture to cope with temperature variations. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail |
Including inductance in static timing analysis. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De |
Formal derivation of optimal active shielding for low-power on-chip buses. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Masud H. Chowdhury, Yehea I. Ismail |
Realistic scalability of noise in dynamic circuits. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De |
Reducing the Data Switching Activity on Serial Link Buses. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Keith A. Bowman, James Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De |
Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
intra-die variations, multi-cycle interconnect, parameter fluctuations, time borrowing, interconnect, parameter variations, within-die variations, variation tolerant |
| 1 | Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail |
Power density minimization for highly-associative caches in embedded processors. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
cache, embedded processor, leakage power, temperature |
| 1 | Gang Qu, Yehea I. Ismail, Narayanan Vijaykrishnan, Hai Zhou (eds.) |
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006 |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP BibTeX RDF |
|
| 1 | Frank Huebbers, Ali Dasdan, Yehea I. Ismail |
Computation of accurate interconnect process parameter values for performance corners under process variations. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
sorners, delay, interconnect, STA, variations |
| 1 | Ja Chun Ku, Yehea I. Ismail |
Area optimization for leakage reduction and thermal stability in nanometer scale technologies. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | DiaaEldin Khalil, Yehea I. Ismail |
Optimum sizing of power grids for IR drop. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De |
Reducing the data switching activity of serialized datastreams. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou |
A timing dependent power estimation framework considering coupling. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail |
Importance of volume discretization of single and coupled interconnects. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack |
FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling. |
ICCD |
2006 |
DBLP BibTeX RDF |
|
| 1 | Maged Ghoneima, Yehea I. Ismail |
Optimum positioning of interleaved repeaters in bidirectional buses. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail |
Weibull-based analytical waveform model. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail |
Realizable reduction of interconnect circuits including self and mutual inductances. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | John Lach, Gang Qu, Yehea I. Ismail (eds.) |
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005 |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP BibTeX RDF |
|
| 1 | Noha H. Mahmoud, Maged Ghoneima, Yehea I. Ismail |
Physical limitations on the bit-rate of on-chip interconnects. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
damping factor, delay, interconnects, bit-rate |
| 1 | Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail |
Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files. |
DSN |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ja Chun Ku, Serkan Ozdemir, Gokhan Memik, Yehea I. Ismail |
Thermal Management of On-Chip Caches Through Power Density Minimization. |
MICRO |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu |
Piece-wise approximations of RLCK circuit responses using moment matching. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
RC, RLCK circuits, interconnect timing analysis, moments, RLC |
| 1 | Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail |
Statistical static timing analysis: how simple can we get? |
DAC |
2005 |
DBLP DOI BibTeX RDF |
statistical static timing analysis (SSTA), process variations |
| 1 | Maged Ghoneima, Yehea I. Ismail |
Accurate decoupling of capacitively coupled buses. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Vivek De |
Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De |
Serial-link bus: a low-power on-chip bus architecture. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Ahmed M. Shebaita, Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail |
Expanding the frequency range of AWE via time shifting. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail |
A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yehea I. Ismail, Chirayu S. Amin |
Computation of signal-threshold crossing times directly from higher order moments. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Maged Ghoneima, Yehea I. Ismail |
Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Shizhong Mei, Yehea I. Ismail |
Modeling skin and proximity effects with reduced realizable RL circuits. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP BibTeX RDF |
|
| 1 | Maged Ghoneima, Yehea I. Ismail |
Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
low power, interconnects, buses, coupling capacitance |
| 1 | Masud H. Chowdhury, Yehea I. Ismail |
Possible Noise Failure Modes in Static and Dynamic Circuits. |
IWSOC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Maged Ghoneima, Yehea I. Ismail |
Effect of relative delay on the dissipated energy in coupled interconnects. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Maged Ghoneima, Yehea I. Ismail |
Low power coupling-based encoding for on-chip buses. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Daniel Dai, Yehea I. Ismail, Wei Wang 0003, Hanif M. Ladak |
Powder-based fabrication techniques for single-wall carbon nanotube circuits. |
ISCAS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Maged Ghoneima, Yehea I. Ismail |
Formal derivation of optimal active shielding for low-power on-chip buses. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Yehea I. Ismail, Chirayu S. Amin |
Computation of signal threshold crossing times directly from higher order moments. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail |
Modeling unbuffered latches for timing analysis. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Yehea I. Ismail, Eby G. Friedman |
On the Extraction of On-Chip Inductance. |
Journal of Circuits, Systems, and Computers |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Yehea I. Ismail |
Improved model-order reduction by using spacial information in moments. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Shizhong Mei, Chirayu S. Amin, Yehea I. Ismail |
Efficient model order reduction including skin effect. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
simulation, VLSI, model order reduction, skin effect, RLC |
| 1 | Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail |
Realizable RLCK circuit crunching. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
crunching, simulation, interconnect, passive, realizable, model order reduction |
| 1 | Maged Ghoneima, Yehea I. Ismail |
Optimum positioning of interleaved repeaters In bidirectional buses. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
delay, interconnect, noise, repeaters, buses |
| 1 | Masud H. Chowdhury, Yehea I. Ismail |
Analysis of Coupling Noise in Dynamic Circuit. |
IWSOC |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Shizhong Mei, Yehea I. Ismail |
Modeling skin effect with reduced decoupled R-L circuits. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter |
Realizable reduction of RLC circuits using node elimination. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Noha H. Mahmoud, Yehea I. Ismail |
Accurate rise time and overshoots estimation in RLC interconnects. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail |
Weibull Based Analytical Waveform Model. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Yehea I. Ismail, Eby G. Friedman, José Luis Neves |
Inductance Effects in RLC Trees. |
Journal of Circuits, Systems, and Computers |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Yehea I. Ismail, Eby G. Friedman |
DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Yehea I. Ismail |
On-chip inductance cons and pros. |
IEEE Trans. VLSI Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Yehea I. Ismail, Byron Krauter |
Guest editorial: special issue on on-chip inductance in high-speed integrated circuits. |
IEEE Trans. VLSI Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Yehea I. Ismail |
Evaluating noise pulses in RC networks due to capacitive coupling. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Masud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter |
Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Yehea I. Ismail |
Efficient model order reduction via multi-node moment matching. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Yehea I. Ismail, Eby G. Friedman, José Luis Neves |
Exploiting the on-chip inductance in high-speed clock distribution networks. |
IEEE Trans. VLSI Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Yehea I. Ismail, Eby G. Friedman, José Luis Neves |
Equivalent Elmore delay for RLC trees. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
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