Search results for "Yici Cai"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Wenchao Gao, Qiang Zhou, Xu Qian, Yici Cai	A DyadicCluster method used for nonlinear placement.	ISQED	2012	DBLP DOI BibTeX RDF
1	Hailong Yao, Yici Cai, Qiang Gao	LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie	Thermal-aware power network design for IR drop reduction in 3D ICs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Qiang Zhou, Jin Shi, Bin Liu 0007, Yici Cai	Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Zhigang Hao, Ruijing Shen, Sheldon X.-D. Tan, Bao Liu, Guoyong Shi, Yici Cai	Statistical full-chip dynamic power estimation considering spatial correlations.	ISQED	2011	DBLP DOI BibTeX RDF
1	Zhongdong Qi, Qiang Zhou, Yanming Jia, Yici Cai, Zhuoyuan Li, Hailong Yao	A novel fine-grain track routing approach for routability and crosstalk optimization.	ISQED	2011	DBLP DOI BibTeX RDF
1	Qiang Gao, Hailong Yao, Qiang Zhou, Yici Cai	A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits.	ISQED	2011	DBLP DOI BibTeX RDF
1	Shuzhe Zhou, Hailong Yao, Qiang Zhou, Yici Cai	Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Limin Zhu, Jinian Bian, Qiang Zhou, Yici Cai	A fast recursive detailed routing algorithm for hierarchical FPGAs.	CSCWD	2011	DBLP DOI BibTeX RDF
1	Fan Yang, Hailong Yao, Qiang Zhou, Yici Cai	SIAR: splitting-graph-based interactive analog router.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin-Ngai Sze	Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou	PowerRush: A linear simulator for power grid.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi	Fast poisson solver preconditioned method for robust power grid analysis.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Ruijing Shen, Sheldon X.-D. Tan, Jian Cui, Wenjian Yu, Yici Cai, Gengsheng Chen	Variational Capacitance Extraction and Modeling Based on Orthogonal Polynomial Method.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Yin Shen, Qiang Zhou, Yici Cai, Xianlong Hong	ECP- and CMP-Aware Detailed Routing Algorithm for DFM.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Yici Cai, Jin Shi, Shuai Li	Optimization of via distribution and stacked via in multi-layered P/G networks.	Integration	2010	DBLP DOI BibTeX RDF
1	Ruijing Shen, Sheldon X.-D. Tan, Ning Mi, Yici Cai	Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.	Integration	2010	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Wei Chen, Yongqiang Lu, Qiang Zhou, Jiang Hu	Useful clock skew optimization under a multi-corner multi-mode design framework.	ISQED	2010	DBLP DOI BibTeX RDF
1	Qiang Gao, Yin Shen, Yici Cai, Hailong Yao	Analog circuit shielding routing algorithm based on net classification.	ISLPED	2010	DBLP DOI BibTeX RDF	analog routing, shielding routing, A* algorithm
1	Limin Zhu, Qiang Zhou, Yici Cai, Jinian Bian	An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA.	CSCWD	2010	DBLP DOI BibTeX RDF
1	Jin Shi, Yici Cai	Scaling power/ground solvers on multi-core with memory bandwidth awareness.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	power/ground solver, multi-core
1	Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Yici Cai	Efficient model reduction of interconnects via double gramians approximation.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai	Efficient power grid integrity analysis using on-the-fly error check and reduction.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Fan Yang, Yici Cai, Qiang Zhou, Jiang Hu	SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal.	DATE	2010	DBLP BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	A single layer zero skew clock routing in X architecture.	Science in China Series F: Information Sciences	2009	DBLP DOI BibTeX RDF	single layer, X architecture, zero skew, clock routing
1	Qiang Zhou, Xin Zhao, Yici Cai, Xianlong Hong	An MTCMOS technology for low-power physical design.	Integration	2009	DBLP DOI BibTeX RDF
1	Dawei Liu, Qiang Zhou, Jinian Bian, Yici Cai, Xianlong Hong	Cell shifting aware of wirelength and overlap.	ISQED	2009	DBLP DOI BibTeX RDF
1	Jin Shi, Yici Cai, Wenting Hou, Liwei Ma, Sheldon X.-D. Tan, Pei-Hsin Ho, Xiaoyi Wang	GPU friendly fast Poisson solver for structured power grid network analysis.	DAC	2009	DBLP DOI BibTeX RDF	P/G network, fast Poisson solver, GPU
1	Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Xiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Jacob Relles	An efficient decoupling capacitance optimization using piecewise polynomial models.	DATE	2009	DBLP BibTeX RDF
1	Jinpeng Zhao, Qiang Zhou, Yici Cai	Fast congestion-aware timing-driven placement for island FPGA.	DDECS	2009	DBLP DOI BibTeX RDF
1	Hui Dai, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong	Fast placement for large-scale hierarchical FPGAs.	CAD/Graphics	2009	DBLP DOI BibTeX RDF
1	Yun Huang, Qiang Zhou, Yici Cai, Haixia Yan	A thermal-driven force-directed floorplanning algorithm for 3D ICs.	CAD/Graphics	2009	DBLP DOI BibTeX RDF
1	Xiaoyi Wang, Yici Cai, Qiang Zhou, Sheldon X.-D. Tan, Thom Jefferson A. Eguia	Decoupling capacitance efficient placement for reducing transient power supply noise.	ICCAD	2009	DBLP BibTeX RDF
1	Yanming Jia, Yici Cai, Xianlong Hong	Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong	Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Low Power Gated Clock Tree Driven Placement.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong	Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Yici Cai, Qiang Zhou, Xianlong Hong, Rui Shi, Yang Wang	Application of optical proximity correction technology.	Science in China Series F: Information Sciences	2008	DBLP DOI BibTeX RDF	layout, rules-based, OPC, model-based, IC
1	Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Yici Cai, Le Kang, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan	Random Walk Guided Decap Embedding for Power/Ground Network Optimization.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	Zero skew clock routing in X-architecture based on an improved greedy matching algorithm.	Integration	2008	DBLP DOI BibTeX RDF
1	Yici Cai, Jin Shi, Zhu Pan, Xianlong Hong, Sheldon X.-D. Tan	Large scale P/G grid transient simulation using hierarchical relaxed approach.	Integration	2008	DBLP DOI BibTeX RDF
1	Yin Shen, Yici Cai, Qiang Zhou, Xianlong Hong	DFM Based Detailed Routing Algorithm for ECP and CMP.	ISQED	2008	DBLP DOI BibTeX RDF	ECP, CMP, DFM, detailed routing
1	Xing Wei, Juanjuan Chen, Qiang Zhou, Yici Cai, Jinian Bian, Xianlong Hong	MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation.	FPL	2008	DBLP DOI BibTeX RDF
1	Yibo Wang, Yici Cai, Xianlong Hong	A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Yanming Jia, Yici Cai, Xianlong Hong	Full-chip routing system for reducing Cu CMP & ECP variation.	SBCCI	2008	DBLP DOI BibTeX RDF	electroplating, routing, chemical mechanical polishing
1	Liangpeng Guo, Yici Cai, Qiang Zhou, Le Kang, Xianlong Hong	A novel performance driven power gating based on distributed sleep transistor network.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	physical design, power-gating, sleep transistors
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity and register placement aware gated clock network design.	ISPD	2008	DBLP DOI BibTeX RDF	gated clock tree, low power, placement
1	Shuai Li, Jin Shi, Yici Cai, Xianlong Hong	Vertical via design techniques for multi-layered P/G networks.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong	Heuristic power/ground network and floorplan co-design method.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian	Low power clock buffer planning methodology in F-D placement for large scale circuit design.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong	Leakage power optimization for clock network using dual-Vth technology.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Gate planning during placement for gated clock network.	ICCD	2008	DBLP DOI BibTeX RDF
1	Yibo Wang, Yici Cai, Xianlong Hong, Yi Zou	Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Yici Cai, Bin Liu 0007, Qiang Zhou, Xianlong Hong	Voltage Island Generation in Cell Based Dual-Vdd Design.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Jin Shi, Yici Cai, Sheldon X.-D. Tan, Jeffrey Fan, Xianlong Hong	Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Qiang Zhou, Yici Cai, Duo Li, Xianlong Hong	A Yield-Driven Gridless Router.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	gridless routing, integrated circuit layout, critical area, design for yield
1	Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu	An efficient quadratic placement based on search space traversing technology.	Integration	2007	DBLP DOI BibTeX RDF
1	Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Partitioning-based decoupling capacitor budgeting via sequence of linear programming.	Integration	2007	DBLP DOI BibTeX RDF
1	Yici Cai, Bin Liu 0007, Jin Shi, Qiang Zhou, Xianlong Hong	Power Delivery Aware Floorplanning for Voltage Island Designs.	ISQED	2007	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu	Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture.	ISQED	2007	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Hailong Yao, Yici Cai, Xianlong Hong	CMP-aware Maze Routing Algorithm for Yield Enhancement.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Yanming Jia, Yici Cai, Xianlong Hong	Dummy fill aware buffer insertion during routing.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	routing, VLSI, DFM, buffer insertion, dummy fill
1	Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong	New timing and routability driven placement algorithms for FPGA synthesis.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	congestion driven placement, physical synthesis, timing driven placement, net weight
1	Xinjie Wei, Yici Cai, Xianlong Hong	Physical aware clock skew rescheduling.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	skew rescheduling, process variations, clock skew
1	Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan	Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach.	ASP-DAC	2007	DBLP DOI BibTeX RDF	programming method, decoupling capacitor budgeting algorithm, random walk approach, decap budgeting algorithm, power ground network design, isolation property, decap optimization process, leakage currents optimization algorithm, refined leakage model, heuristic method
1	Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang	Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos.	ASP-DAC	2007	DBLP DOI BibTeX RDF	stochastic parameterized model order reduction, Hermite polynomial chaos, stochastic model order reduction algorithm, stochastic Hermite polynomials, stochastic interconnect analysis, nonGaussian input variations, implicit system representation, block matrix structure, Monte Carlo methods, linear equations
1	Liangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong	Logic and Layout Aware Voltage Island Generation for Low Power Design.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Statistical model order reduction for interconnect circuits considering spatial correlations.	DATE	2007	DBLP DOI BibTeX RDF
1	Yanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai	Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Xinjie Wei, Yici Cai, Xianlong Hong	Effective Acceleration of Iterative Slack Distribution Process.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Le Kang, Yici Cai, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan, Xiaoyi Wang	Simultaneous Switching Noise Consideration for Power/Ground Network Optimization.	CAD/Graphics	2007	DBLP DOI BibTeX RDF
1	Ning Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong	Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Xiaoyi Wang, Zhu Pan, Jingjing Fu	Time-domain analysis methodology for large-scale RLC circuits and its applications.	Science in China Series F: Information Sciences	2006	DBLP DOI BibTeX RDF	RLC circuits, analog circuit analysis, P/G networks, algorithm complexity, time-domain analysis
1	Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong	Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Xinjie Wei, Yici Cai, Meng Zhao, Xianlong Hong	Legitimate Skew Clock Routing with Buffer Insertion.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	legitimate skew, buffer insertion, clock routing
1	Yici Cai, Bin Liu 0007, Yan Xiong, Qiang Zhou, Xianlong Hong	Priority-Based Routing Resource Assignment Considering Crosstalk.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	track reservation, routing, VLSI, crosstalk, resource assignment
1	Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming.	ISQED	2006	DBLP DOI BibTeX RDF
1	Xinjie Wei, Yici Cai, Xianlong Hong	Clock Skew Scheduling Under Process Variations.	ISQED	2006	DBLP DOI BibTeX RDF
1	Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong	High accurate pattern based precondition method for extremely large power/ground grid analysis.	ISPD	2006	DBLP DOI BibTeX RDF	pattern, iterative method, precondition, PCG
1	Bin Liu 0007, Yici Cai, Qiang Zhou, Xianlong Hong	Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong	Efficient early stage resonance estimation techniques for C4 package.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Qiang Zhou, Yi Zou, Yici Cai, Xianlong Hong	Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Xianlong Hong, Yici Cai, Hailong Yao, Duo Li	DFM-aware Routing for Yield Enhancement.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Hailong Yao, Yici Cai, Xianlong Hong	Congestion-driven W-shape multilevel full-chip routing framework.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Lijuan Luo, Qiang Zhou, Yici Cai, Xianlong Hong, Yibo Wang	A novel technique integrating buffer insertion into timing driven placement.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Weixiang Shen, Yici Cai, Jiang Hu, Xianlong Hong, Bing Lu	High performance clock routing in X-architecture.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong	A novel low-power physical design methodology for MTCMOS.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Yibo Wang, Yici Cai, Xianlong Hong	Performance and power aware buffered tree construction.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Hailong Yao, Subarna Sinha, Charles Chiang, Xianlong Hong, Yici Cai	Efficient process-hotspot detection using range pattern matching.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan	A Fast Delay Computation for the Hybrid Structured Clock Network.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Yongqiang Lu, Chin-Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu	Navigating Register Placement for Low Power Clock Network Design.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Bin Liu 0007, Yici Cai, Qiang Zhou, Xianlong Hong	Crosstalk and Congestion Driven Layer Assignment Algorithm.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Yici Cai, Yan Xiong, Xianlong Hong, Yi Liu	Reliable buffered clock tree routing algorithm with process variation tolerance.	Science in China Series F: Information Sciences	2005	DBLP DOI BibTeX RDF
1	Yici Cai, Jin Shi, Zuying Luo, Xianlong Hong	Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	power/ground network, mesh tree hybrid, multi-source, Choleskey decomposition, fast variable elimination, simulation, VLSI
1	Yici Cai, Xin Zhao, Qiang Zhou, Xianlong Hong	Shielding Area Optimization Under the Solution of Interconnect Crosstalk.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	middle shield insertion, crosstalk, inductive coupling

Publications of "Yici Cai" ( http://dblp.L3S.de/Authors/Yici_Cai )