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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 7 occurrences of 6 keywords
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Results
Found 11 publication records. Showing 11 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 2 | Yifan Liu, Lawrence M. Wein |
A Queueing Analysis to Determine How Many Additional Beds Are Needed for the Detention and Removal of Illegal Aliens.  |
Management Science  |
2008 |
DBLP DOI BibTeX RDF |
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| 2 | Yifan Liu, Zheng Su |
Generalized Rayleigh Quotient Shift Strategy in QR Algorithm for Eigenvalue Problems.  |
NAA  |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Daniel K. Beece, Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov, Yifang Liu |
Transistor sizing of custom high-performance digital circuits with parametric yield considerations.  |
DAC  |
2010 |
DBLP DOI BibTeX RDF |
custom circuits, optimization |
| 1 | Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li |
Accurate clock mesh sizing via sequential quadraticprogramming.  |
ISPD  |
2010 |
DBLP DOI BibTeX RDF |
optimization, sequential quadratic programming |
| 1 | Yifang Liu, Jiang Hu |
A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Yifang Liu, Jiang Hu |
GPU-based parallelization for fast circuit optimization.  |
DAC  |
2009 |
DBLP DOI BibTeX RDF |
VLSI circuit optimization, parallel computing, GPU |
| 1 | Yifang Liu, Jiang Hu |
A new algorithm for simultaneous gate sizing and threshold voltage assignment.  |
ISPD  |
2009 |
DBLP DOI BibTeX RDF |
threshold voltage assignment, gate sizing |
| 1 | Yifang Liu, Rupesh S. Shelar, Jiang Hu |
Delay-optimal simultaneous technology mapping and placement with applications to timing optimization.  |
ICCAD  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Yifang Liu, Jiang Hu, Weiping Shi |
Multi-scenario buffer insertion in multi-core processor designs.  |
ISPD  |
2008 |
DBLP DOI BibTeX RDF |
multi-core design, buffer insertion |
| 1 | Yifang Liu, Jiang Hu, Weiping Shi |
Buffering Interconnect for Multicore Processor Designs.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Jiquan Zhou, Xiangli Liu, Xiaozhong Yang, Yifang Liu |
Novel soliton-like and multi-solitary wave solutions of (3 + 1)-dimensional Burgers equation.  |
Applied Mathematics and Computation  |
2008 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #11 of 11 (20 per page; Change: )
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