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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 14 occurrences of 14 keywords
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Results
Found 35 publication records. Showing 35 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu |
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Cheng-Chen Lin, Ruei-Ting Hung |
Lossless Hyperspectral Image Compression System-Based on HW/SW Codesign. |
Embedded Systems Letters |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Chen Lin, Yin-Tsung Hwang |
Lossless Compression of Hyperspectral Images Using Adaptive Prediction and Backward Search Schemes. |
J. Inf. Sci. Eng. |
2011 |
DBLP BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Feng-Ming Chang, Shin-Wen Chen |
Low complexity baseband transceiver design for narrow band power line communication. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
Low Power Pulse Generator Design Using Hybrid Logic. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Wei-Da Chen |
MMSE-QR factorization systolic array design for applications in MIMO signal detections. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Cheng-Chen Lin, Yin-Tsung Hwang, Yi-Chen Chang, Jiun-Jiang Chen, Ming-Wei Liu |
Lossless Coding of Multiband Images Using Interband Data Correlation and Error Feedback Prediction Scheme. |
IIH-MSP |
2010 |
DBLP DOI BibTeX RDF |
multiband images, context matching, lossless compression |
| 1 | Yin-Tsung Hwang, Hua-Hsin Luo |
Automatic IP Interface Synthesis Supporting Multi-layer Communication Protocols in SoC Designs. |
IAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Peng Chou, Chien-Hsing Wu, Tsung-Hsien Liu, Yin-Tsung Hwang |
Space-Frequency-Coded MIMO OFDM Receivers Based on Gaussian Message Passing. |
ICC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
Low Complexity Dual-Mode Pulse Generator Designs. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Wei-Da Chen |
A low complexity complex QR factorization design for signal detection in MIMO OFDM systems. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Yin-Tsung Hwang, Jun-Yen Chen, Jun-Jieh Chiu |
HW/SW Auto-Coupling for Fast IP Integration in SoC Designs. |
ICESS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Chen Lin, Yin-Tsung Hwang, Kwan-Hsun Tseng, Shao-Wen Chen |
Wavelet Based Lossless Video Compression Using Motion Compensated Temporal Filtering. |
SiPS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu |
Low Power Multipliers Using Enhenced Row Bypassing Schemes. |
SiPS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Jiun-Yan Chen, Ming-Hwa Sheu |
Automatic Generation of Programmable Parallel CRC & Scrambler Designs. |
SiPS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu |
Low Power Multiplier Designs Based on Improved Column Bypassing Schemes. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho |
A high speed and energy efficient full adder design using complementary & level restoring carry logic. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Tai-Yi Huang, Chung-Ta King, Youn-Long Steve Lin, Yin-Tsung Hwang |
The embedded software consortium of taiwan. |
ACM Trans. Embedded Comput. Syst. |
2005 |
DBLP DOI BibTeX RDF |
educational curricula, Embedded software, integrated circuit design |
| 1 | Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen |
VLSI architectural design tradeoffs for sliding-window log-MAP decoders. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Chen-Yu Tsai, Cheng-Chen Lin |
Block-wise adaptive modulation for OFDM WLAN systems. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang |
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m). |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
Stein's algorithm, Euclid's algorithm, Finite field, systolic array, division |
| 1 | Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen, Hsin-Fu Lo |
VLSI architecture exploration for sliding-window Log-MAP decoders. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Kuo-Wei Liao, Chien-Hsing Wu |
FPGA realization of an OFDM frame synchronization design for dispersive channels. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Cheng-Ji Chang, Bor-Liang Chen |
A rapid prototyping embedded system platform and its HW/SW communication interface generation and verification. |
APCCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang |
An area-efficient systolic division circuit over GF(2/sup m/) for secure communication. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang |
Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Jih-Cheng Han, Jing-Yi Liu |
Design and implementation of channel equalizers for block transmission systems. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Yuan-Hung Wang, Jer-Sho Hwang |
Rapid Prototyping of Hardware / Software Codesign for Embedded Signal Processing. |
J. Inf. Sci. Eng. |
1998 |
DBLP BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Jer-Sho Hwang |
Simulated Evolution Based Parallel Code Generation for Programmable DSP Processors. |
J. Inf. Sci. Eng. |
1998 |
DBLP BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Yuan-Hung Wang |
Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System. (PDF / PS) |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Long Su, Yin-Tsung Hwang |
Distributed arithmetic-based architectures for high speed IIR filter design. (PDF / PS) |
ICPADS |
1996 |
DBLP DOI BibTeX RDF |
high speed IIR filter, pipelining techniques, SPDM technology, parallel processing, parallel architectures, digital arithmetic, recursion, recursive filters, Distributed Arithmetic, IIR filters, DSP applications |
| 1 | Yin-Tsung Hwang, Yu Hen Hu |
A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays. |
VLSI Signal Processing |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Yin-Tsung Hwang, Yu Hen Hu |
MSSM - A design aid for multi-stage systolic mapping. |
VLSI Signal Processing |
1992 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #35 of 35 (100 per page; Change: )
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