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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 22 occurrences of 18 keywords
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Results
Found 34 publication records. Showing 34 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Zhaobo Zhang, Xrysovalantis Kavousianos, Yan Luo, Yiorgos Tsiatouhas, Krishnendu Chakrabarty |
Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches.  |
European Test Symposium  |
2011 |
DBLP DOI BibTeX RDF |
Multi-Mode Power Switches, DFT for Multicore Chips, Static Power Management, Testing, Voltage-Control Oscillator |
| 1 | Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas |
A Robust and Reconfigurable Multi-mode Power Gating Architecture. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty |
A BIST scheme for testing and repair of multi-mode power switches. |
IOLTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas |
A Built-In-Test Circuit for RF Differential Low Noise Amplifiers. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Yiannis Moisiadis, Yiorgos Tsiatouhas |
A Receiver Circuit for Low-Swing Interconnect Schemes. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Themistoklis Haniotakis, Zaher Owda, Yiorgos Tsiatouhas |
Memory-Less Pipeline Dynamic Circuit Design Technique. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas |
A Build-In Self-Test technique for RF Mixers. |
DDECS |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | S. Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni |
Timing error tolerance in nanometer ICs. |
IOLTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yiorgos Sfikas, Yiorgos Tsiatouhas |
Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing. |
DDECS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni |
A Current Mode, Parallel, Two-Rail Code Checker. |
IEEE Trans. Computers |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou |
Testable Designs of Multiple Precharged Domino Circuits. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Y. Tsiatouhas, Angela Arapoyanni |
High fan-in differential current mirror logic. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni |
A Built-In Self-Test Scheme for Differential Ring Oscillators. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | A. Rao, Th. Haniotakis, Y. Tsiatouhas, H. Djemil |
The Use of Pre-Evaluation Phase in Dynamic CMOS Logic. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
Pre-Evaluation, Low Power, Domino |
| 1 | Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou |
Fast, Parallel Two-Rail Code Checker with Enhanced Testability. |
IOLTS |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni |
A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators. |
J. Electronic Testing |
2004 |
DBLP DOI BibTeX RDF |
Radio Frequency (RF) Testing, Design for Testability (DFT), Voltage Controlled Oscillator (VCOs) |
| 1 | Sotirios Matakias, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis |
A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs. |
J. Electronic Testing |
2004 |
DBLP DOI BibTeX RDF |
soft and timing errors, monitoring circuits, concurrent testing, time redundancy |
| 1 | Sotirios Matakias, Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni |
Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications . |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky |
A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations. |
IOLTS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni |
An Embedded IDDQ Testing Architecture and Technique. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
IEEE 1149.1, Design for Testability (DFT), Boundary Scan, IDDQ Testing |
| 1 | Y. Tsiatouhas, Sotirios Matakias, Angela Arapoyanni, Th. Haniotakis |
A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs. |
IOLTS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni |
A new technique for IDDQ testing in nanometer technologies. |
Integration |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni |
Extending the Viability of IDDQ Testing in the Deep Submicron Era. (PDF / PS) |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis |
SRAM oriented memory sense amplifier design in 0.18 /spl mu/m CMOS technology. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis |
A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing. |
IOLTW |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou |
Concurrent Detection of Soft Errors Based on Current Monitoring. |
IOLTW |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | G. Kamoulakos, A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni |
Management of charge pump circuits. |
Integration |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou |
On Testability of Multiple Precharged Domino Logic. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos |
A Versatile Built-In Self-Test Scheme for Delay Fault Testing. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos |
A Compact Built-In Current Sensor for IDDQ Testing. |
IOLTW |
2000 |
DBLP DOI BibTeX RDF |
Bridging and Stuck-on fault testability, Design for testability, DFT, IDDQ testing, Built in current sensors, BICS, Current monitoring |
| 1 | Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis |
On Path Delay Fault Testing of Multiplexer - Based Shifters. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas |
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Y. Tsiatouhas, Th. Haniotakis |
A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing. (PDF / PS) |
DFT |
1999 |
DBLP DOI BibTeX RDF |
Built-In Self Test, Delay Fault Testing |
| 1 | Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas |
C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. (PDF / PS) |
DFT |
1998 |
DBLP DOI BibTeX RDF |
robustly delay fault testable circuits, path delay faults, C-testability, Iterative-logic-arrays |
Displaying result #1 - #34 of 34 (100 per page; Change: )
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