Search results for "Yiran Chen"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Yiran Chen, Hai Li, Xiaobin Wang, Wenzhong Zhu, Wei Xu, Tong Zhang	A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Xiang Chen, Jian Zeng, Yiran Chen, Wei Zhang, Hai Li	Fine-grained dynamic voltage scaling on OLED display.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Yiran Chen, Yaojun Zhang, Peiyuan Wang	Probabilistic design in spintronic memory and logic circuit.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Bo Zhao, Jun Yang 0002, Youtao Zhang, Yiran Chen, Hai Li	Architecting a common-source-line array for bipolar non-volatile memory devices.	DATE	2012	DBLP BibTeX RDF
1	Xiuyuan Bi, Chao Zhang, Hai Li, Yiran Chen, Robinson E. Pino	Spintronic memristor based temperature sensor design with CMOS current reference.	DATE	2012	DBLP BibTeX RDF
1	Yaojun Zhang, Xiaobin Wang, Yong Li, Alex K. Jones, Yiran Chen	Asymmetry of MTJ switching and its implication to STT-RAM designs.	DATE	2012	DBLP BibTeX RDF
1	Miao Hu, Hai Helen Li, Yiran Chen, Xiaobin Wang	Spintronic Memristor: Compact Model and Statistical Analysis.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Xiangyu Dong, Xiaoxia Wu, Yuan Xie, Yiran Chen, Hai Helen Li	Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation.	IET Computers & Digital Techniques	2011	DBLP DOI BibTeX RDF
1	Wei Xu, Hongbin Sun, Xiaobin Wang, Yiran Chen, Tong Zhang	Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM).	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Yiran Chen, Weng-Fai Wong, Hai Li, Cheng-Kok Koh	Processor caches with multi-level spin-transfer torque ram cells.	ISLPED	2011	DBLP BibTeX RDF
1	Ping Zhou, Bo Zhao, Youtao Zhang, Jun Yang 0002, Yiran Chen	MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache Replacement.	PACT	2011	DBLP DOI BibTeX RDF
1	Peiyuan Wang, Xiang Chen, Yiran Chen, Hai Helen Li, Seung H. Kang, Xiaochun Zhu, Wenqing Wu	A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis.	CICC	2011	DBLP DOI BibTeX RDF
1	Miao Hu, Hai Li, Yiran Chen, Xiaobin Wang, Robinson E. Pino	Geometry variations analysis of TiO2 thin-film and spintronic memristors.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Yiran Chen, Hai Li	Emerging sensing techniques for emerging memories.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Yi-Chung Chen, Hai Li, Yiran Chen, Robinson E. Pino	3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers.	DATE	2011	DBLP DOI BibTeX RDF
1	Yaojun Zhang, Xiaobin Wang, Yiran Chen	STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Chun Jason Xue, Youtao Zhang, Yiran Chen, Guangyu Sun, J. Jianhua Yang, Hai Li	Emerging non-volatile memories: opportunities and challenges.	CODES+ISSS	2011	DBLP DOI BibTeX RDF
1	Yiran Chen, Xiaobin Wang, Hai Li, Haiwen Xi, Yuan Yan, Wenzhong Zhu	Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy	Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Wei Xu, Tong Zhang, Yiran Chen	Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Yiran Chen, Wei Tian, Hai Li, Xiaobin Wang, Wenzhong Zhu	Scalability of PCMO-based resistive switch device in DSM technologies.	ISQED	2010	DBLP DOI BibTeX RDF
1	Yuan Zhang, Jie Tang, Jimeng Sun, Yiran Chen, Jinghai Rao	MoodCast: Emotion Prediction via Dynamic Continuous Factor Graph Model.	ICDM	2010	DBLP DOI BibTeX RDF
1	Yiran Chen, Hai Li, Xiaobin Wang, Wenzhong Zhu, Wei Xu, Tong Zhang	Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM.	ISLPED	2010	DBLP DOI BibTeX RDF	STT-RAM, emerging memory, spintronic
1	Dimin Niu, Yiran Chen, Yuan Xie	Low-power dual-element memristor based memory design.	ISLPED	2010	DBLP DOI BibTeX RDF	memristor, low power, nonvolatile memory
1	Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie	Impact of process variations on emerging memristor.	DAC	2010	DBLP DOI BibTeX RDF	memristor, process variation, nonvolatile memory
1	Yiran Chen, Hai Li, Xiaobin Wang, Wenzhong Zhu, Wei Xu, Tong Zhang	A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM).	DATE	2010	DBLP BibTeX RDF
1	Xiaobin Wang, Yiran Chen	Spintronic memristor devices and application.	DATE	2010	DBLP BibTeX RDF
1	Guangyu Sun, Yongsoo Joo, Yibo Chen, Dimin Niu, Yuan Xie, Yiran Chen, Hai Li	A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.	HPCA	2010	DBLP DOI BibTeX RDF
1	Zhenyu Sun, Hai Li, Yiran Chen, Xiaobin Wang	Variation tolerant sensing scheme of Spin-Transfer Torque Memory for yield improvement.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li	Tolerating process variations in large, set-associative caches: The buddy cache.	TACO	2009	DBLP DOI BibTeX RDF	caches, Processor architectures, fault recovery, memory structures
1	Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh	Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Hai Li, Haiwen Xi, Yiran Chen, John Stricklin, Xiaobin Wang, Tong Zhang	Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration.	ISVLSI	2009	DBLP DOI BibTeX RDF
1	Wei Xu, Yiran Chen, Xiaobin Wang, Tong Zhang	Improving STT MRAM storage density through smaller-than-worst-case transistor sizing.	DAC	2009	DBLP DOI BibTeX RDF	STT MRAM, defect tolerance, transistor sizing
1	Hai Li, Yiran Chen	An overview of non-volatile memory technology and the implication for tools and architectures.	DATE	2009	DBLP BibTeX RDF
1	Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen	A novel architecture of the 3D stacked MRAM L2 cache for CMPs.	HPCA	2009	DBLP DOI BibTeX RDF
1	Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, Hai Li	The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies.	ICCD	2009	DBLP DOI BibTeX RDF
1	Yiran Chen, Xiaobin Wang, Hai Li, Harry Liu, Dimitar V. Dimitrov	Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM).	ISQED	2008	DBLP DOI BibTeX RDF
1	Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Hai Helen Li, Yiran Chen	Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.	DAC	2008	DBLP DOI BibTeX RDF	3D stacking, MRAM
1	Wei Xu, Tong Zhang, Yiran Chen	Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen	Statistical Timing Analysis Considering Spatial Correlations.	ISQED	2007	DBLP DOI BibTeX RDF
1	Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh	Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI.	ISLPED	2007	DBLP DOI BibTeX RDF	variable-latency adder (VL-adder), negative bias temperature instability (NBTI)
1	Weng-Fai Wong, Cheng-Kok Koh, Yiran Chen, Hai Li	VOSCH: Voltage scaled cache hierarchies.	ICCD	2007	DBLP DOI BibTeX RDF
1	Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh	SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Yiran Chen, Kaushik Roy, Cheng-Kok Koh	Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Dongku Kang, Yiran Chen, Kaushik Roy	Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis.	ISQED	2005	DBLP DOI BibTeX RDF
1	Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh	Cascaded carry-select adder (C2SA): a new structure for low-power CSA design.	ISLPED	2005	DBLP DOI BibTeX RDF	low-power, carry-select adder
1	Wai-Ching Douglas Lam, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan, Yiran Chen	Statistical based link insertion for robust clock network design.	ICCAD	2005	DBLP BibTeX RDF
1	Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar	DCG: deterministic clock-gating for low-power microprocessor design.	IEEE Trans. VLSI Syst.	2004	DBLP BibTeX RDF
1	Yiran Chen, Kaushik Roy, Cheng-Kok Koh	Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Yiran Chen, Kaushik Roy, Cheng-Kok Koh	Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors.	ISLPED	2003	DBLP DOI BibTeX RDF	power supply noise, inductive noise
1	Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy	Deterministic Clock Gating for Microprocessor Power Reduction.	HPCA	2003	DBLP DOI BibTeX RDF
1	Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, Kaushik Roy	Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods.	DATE	2002	DBLP DOI BibTeX RDF

Publications of "Yiran Chen" ( http://dblp.L3S.de/Authors/Yiran_Chen )