Search results for "Yong Dou"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Rongchun Li, Yong Dou, Yuanwu Lei, Shi-Ce Ni, Song Guo	Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Guiming Wu, Yong Dou, Junqing Sun, Gregory D. Peterson	A High Performance and Memory Efficient LU Decomposer on FPGAs.	IEEE Trans. Computers	2012	DBLP DOI BibTeX RDF
1	Yuanwu Lei, Yong Dou, Jie Zhou	FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Yuanwu Lei, Yong Dou, Jie Zhou, Sufeng Wang	VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic.	FPL	2011	DBLP DOI BibTeX RDF
1	Yuanwu Lei, Yong Dou, Song Guo, Jie Zhou	FPGA Implementation of Variable-Precision Floating-Point Arithmetic.	APPT	2011	DBLP DOI BibTeX RDF
1	Yuanwu Lei, Yong Dou, Li Shen, Jie Zhou, Song Guo	Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA.	ICCD	2011	DBLP DOI BibTeX RDF
1	Fei Xia, Yong Dou, Dan Zhou, Xin Li	Fine-grained parallel RNA secondary structure prediction using SCFGs on FPGA.	Parallel Computing	2010	DBLP DOI BibTeX RDF
1	Fei Xia, Yong Dou, Guo-Qing Lei	Fpqrna: Hardware-Accelerated Qrna Package for noncoding RNA Gene Detecting on FPGA.	J. Bioinformatics and Computational Biology	2010	DBLP DOI BibTeX RDF
1	Yong Dou, Jie Zhou, Guiming Wu, Jingfei Jiang, Yuanwu Lei, Shi-Ce Ni	A Unified Co-Processor Architecture for Matrix Decomposition.	J. Comput. Sci. Technol.	2010	DBLP DOI BibTeX RDF
1	Guiming Wu, Yong Dou, Miao Wang	Automatic synthesis of processor arrays with local memories on FPGAs.	FPT	2010	DBLP DOI BibTeX RDF
1	Guiming Wu, Yong Dou, Miao Wang	High performance and memory efficient implementation of matrix multiplication on FPGAs.	FPT	2010	DBLP DOI BibTeX RDF
1	Guiming Wu, Yong Dou, Gregory D. Peterson	Blocking LU Decomposition for FPGAs.	FCCM	2010	DBLP DOI BibTeX RDF
1	Yong Dou, Yuanwu Lei, Guiming Wu, Song Guo, Jie Zhou, Li Shen	FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing.	ICS	2010	DBLP DOI BibTeX RDF	double-double precision, high precision floating-point multiplication and accumulation (HP-MAC), quad-double precision, FPGA
1	Jinbo Xu, Yong Dou, Zhengbin Pang	A Reconfigurable Architecture for Rotation Invariant Multi-View Face Detection Based on a Novel Two-Stage Boosting Method.	EURASIP J. Adv. Sig. Proc.	2009	DBLP DOI BibTeX RDF
1	Fei Xia, Yong Dou, Xingming Zhou, Xuejun Yang, Jiaqing Xu, Yang Zhang	Fine-grained parallel RNAalifold algorithm for RNA secondary structure prediction on FPGA.	BMC Bioinformatics	2009	DBLP DOI BibTeX RDF
1	Bao-Feng Li, Yong Dou, Haifang Zhou, Xingming Zhou	FPGA Accelerator for Wavelet-Based Automated Global Image Registration.	EURASIP J. Emb. Sys.	2009	DBLP DOI BibTeX RDF
1	Dawei Wang, Sikun Li, Yong Dou	Loop Kernel Pipelining Mapping onto Coarse-Grained Reconfigurable Architecture for Data-Intensive Applications.	JSW	2009	DBLP DOI BibTeX RDF
1	Yong Dou, Guiming Wu, Jinhui Xu, Xingming Zhou	A coarse-grained reconfigurable computing architecture with loop self-pipelining.	Science in China Series F: Information Sciences	2009	DBLP DOI BibTeX RDF	reconfigurable computing, data driven, loop pipelining, register promotion
1	Yong Dou, Jie Zhou, Xiaoyang Chen, Yuanwu Lei, Jinbo Xu	FPGA accelerating three QR decomposition algorithms in the unified pipelined framework.	FPL	2009	DBLP DOI BibTeX RDF
1	Guangming Liu, Fei Xia, Yong Dou, Xin Liu	FPGA-based Memory-efficient Parallel RNA Secondary Structure Prediction Accelerator Using SCFGs.	PDPTA	2009	DBLP BibTeX RDF
1	Yong Dou, Fei Xia, Jingfei Jiang	Fine-grained parallel application specific computing for RNA secondary structure prediction using SCFGS on FPGA.	CASES	2009	DBLP DOI BibTeX RDF	SCFGS, reconfigurable algorithm accelerator, secondary structure prediction, FPGA, RNA
1	Guiming Wu, Yong Dou, Yuanwu Lei, Jie Zhou, Miao Wang, Jingfei Jiang	A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs.	FCCM	2009	DBLP DOI BibTeX RDF
1	Jie Zhou, Yong Dou, Jianxun Zhao, Fei Xia, Yuanwu Lei, Yuxing Tang	A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA.	APPT	2009	DBLP DOI BibTeX RDF
1	Yong Dou, Ralf Gruber, Josef M. Joller (eds.)	Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings	APPT	2009	DBLP DOI BibTeX RDF
1	Jinbo Xu, Yong Dou, YuXing Tang, Xiaodong Wang	Implementation of Rotation Invariant Multi-View Face Detection on FPGA.	APPT	2009	DBLP DOI BibTeX RDF	FPGA, Face Detection, Rotation Invariant, Hardware Architecture, Multi-View
1	Guiming Wu, Miao Wang, Yong Dou, Fei Xia	Exploiting Fine-Grained Pipeline Parallelism for Wavefront Computations on Multicore Platforms.	ICPP Workshops	2009	DBLP DOI BibTeX RDF
1	Fei Xia, Yong Dou, Jiaqing Xu	Families of FPGA-Based Accelerators for BLAST Algorithm with Multi-seeds Detection and Parallel Extension.	BIRD	2008	DBLP DOI BibTeX RDF
1	Yong Dou, Lin Deng, Jinhui Xu, Yi Zheng	DMA Performance Analysis and Multi-core Memory Optimization for SWIM Benchmark on the Cell Processor.	ISPA	2008	DBLP DOI BibTeX RDF
1	Fei Xia, Yong Dou, Jiaqing Xu	Fine-Grained Parallel Zuker Algorithm Accelerator with Storage Optimization on FPGA.	BIOCOMP	2008	DBLP BibTeX RDF
1	Jie Zhou, Yong Dou, Yuanwu Lei, Jinbo Xu, Yazhuo Dong	Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor.	HPCC	2008	DBLP DOI BibTeX RDF
1	Dawei Wang, Sikun Li, Yong Dou	Collaborative hardware/software partition of coarse-grained reconfigurable system using evolutionary ant colony optimization.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Jinbo Xu, Yong Dou, Jie Zhou	Rectangularly Multi-Module Memory System with Table-Based Dynamic Addressing Scheme.	NAS	2008	DBLP DOI BibTeX RDF
1	Fei Xia, Yong Dou, Jinbo Xu	Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension.	ARC	2008	DBLP DOI BibTeX RDF
1	Jie Zhou, Yong Dou, Yuanwu Lei, Yazhuo Dong	Hybrid-Mode Floating-Point FPGA CORDIC Co-processor.	ARC	2008	DBLP DOI BibTeX RDF
1	Jie Zhou, Yazhuo Dong, Yong Dou, Yuanwu Lei	Dynamic Configurable Floating-Point FFT Pipelines and Hybrid-Mode CORDIC on FPGA.	ICESS	2008	DBLP DOI BibTeX RDF
1	Bao-Feng Li, Yong Dou	Subblock-Based BPE Scheme to Conquer Mismatch in Memory Access Pattern.	IIH-MSP	2008	DBLP DOI BibTeX RDF	EBCOT, Bit-plane encoder, Subblock-based sheme, Image compression, JPEG2000
1	Yong Dou, Fei Xia, Xingming Zhou, Xuejun Yang	Fine-grained parallel application specific computing for RNA secondary structure prediction on FPGA.	ICCD	2008	DBLP DOI BibTeX RDF
1	Jinbo Xu, Yong Dou, Junfeng Li, Xingming Zhou, Qiang Dou	FPGA Accelerating Algorithms of Active Shape Model in People Tracking Applications.	DSD	2007	DBLP DOI BibTeX RDF
1	Sikun Li, Dawei Wang, Tun Li, Yong Dou	Distributed Collaborative Partition Method of Reconfigurable SoC Using Ant Colony Optimization.	CSCWD	2007	DBLP DOI BibTeX RDF
1	Bao-Feng Li, Yong Dou	FIDP: A Novel Architecture for Lifting-Based 2D DWT in JPEG2000.	MMM	2007	DBLP DOI BibTeX RDF
1	Yong Dou, Jinbo Xu	FPGA-Accelerated Active Shape Model for Real-Time People Tracking.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF	FPGA, Active Shape Model, People Tracking
1	Yong Dou, Jie Zhou, Yuanwu Lei, Xingming Zhou	FPGA SAR Processor with Window Memory Accesses.	ASAP	2007	DBLP DOI BibTeX RDF
1	Yazhuo Dong, Yong Dou	A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Fei Xia, Yong Dou	Reducing Storage Requirements in Accelerating Algorithm of Global BioSequence Alignment on FPGA.	APPT	2007	DBLP DOI BibTeX RDF	Global BioSequence Alignment, Needleman-Wunsch algorithm, FPGA, Bioinformatics, Hardware Accelerator
1	Xiaodong Yang, Shengmei Mou, Yong Dou	FPGA-Accelerated Molecular Dynamics Simulations: An Overview.	ARC	2007	DBLP DOI BibTeX RDF
1	Yazhuo Dong, Yong Dou, Jie Zhou	Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware.	ARC	2007	DBLP DOI BibTeX RDF
1	Yong Dou, Jinhui Xu, Guiming Wu	The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining.	ARC	2007	DBLP DOI BibTeX RDF
1	Xuejun Yang, Yong Dou, Qingfeng Hu	Progress and Challenges in High Performance Computer Technology.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	high performance computer, supercomputer, massively parallel processing
1	Jinhui Xu, Guiming Wu, Yong Dou, Yazhuo Dong	Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
1	Song Lu, BaoHua Fan, Yong Dou, Xiaodong Yang	Clustering Multicast on Hypercube Network.	HPCC	2006	DBLP DOI BibTeX RDF
1	YuXing Tang, Kun Deng, Xiaodong Wang, Yong Dou, Xingming Zhou	RIMP: Runtime Implicit Predication.	APPT	2005	DBLP DOI BibTeX RDF	runtime execution, RIMP, predication, trace cache
1	Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, Georgi Gaydadjiev	64-bit floating-point FPGA matrix multiplication.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, matrix multiplication, floating-point
1	Yong Dou, Xicheng Lu	LEAP: A Data Driven Loop Engine on Array Processor.	APPT	2003	DBLP DOI BibTeX RDF

Publications of "Yong Dou" ( http://dblp.L3S.de/Authors/Yong_Dou )