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Publications of "Young-Hwan Park" ( http://dblp.L3S.de/Authors/Young-Hwan_Park )

  Author page on DBLP  Author page in RDF  Community of Young-Hwan Park in ASPL-2

Publication years (Num. hits)
2006-2011 (10)
Publication types (Num. hits)
article(3) inproceedings(7)
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The graphs summarize 14 occurrences of 12 keywords

Results
Found 10 publication records. Showing 10 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt A Multi-Granularity Power Modeling Methodology for Embedded Processors. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1Sudeep Pasricha, Young-Hwan Park, Nikil D. Dutt, Fadi J. Kurdahi System-level PVT variation-aware power exploration of on-chip communication architectures. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF PVT variation, on-chip communication architectures, performance exploration, high-level synthesis, power estimation, digital systems
1Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil Dutt Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt Methodology for multi-granularity embedded processor power model generation for an ESL design flow. Search on Bibsonomy CODES+ISSS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF system-on-chip, embedded processor, power modeling, esl
1Kang Yi, Shih-Yang Cheng, Young-Hwan Park, Fadi J. Kurdahi, Ahmed M. Eltawil An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Embedded memory Yield, Defect Map, Memory Error Resilient Design, Video error concealment
1Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt System level power estimation methodology with H.264 decoder prediction IP case study. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park, Rouwaida Kanj, Sani R. Nassif System-Level SRAM Yield Enhancement. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Kang Yi, Kyeong-Hoon Jung, Shih-Yang Cheng, Young-Hwan Park, Fadi J. Kurdahi, Ahmed M. Eltawil Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Low power image filter design, Memory yield enhancement, Memory-error resilient design, H.264 codec, BIST, Embedded memory, BISR
1Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt System-level power-performance trade-offs in bus matrix communication architecture synthesis. Search on Bibsonomy CODES+ISSS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF bus matrix synthesis, system-on-chip, power estimation, communication architectures, power-performance trade-offs
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