Search results for "Yu Wang 0002"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Yu Wang 0002, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang	Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Weichen Liu, Jiang Xu, Xuan Wang, Yu Wang 0002, Wei Zhang 0012, Yaoyao Ye, Xiaowen Wu, Mahdi Nikdast, Zhehui Wang	A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Wulong Liu, Yu Wang 0002, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang	On-chip hybrid power supply system for wireless sensor nodes.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Di Wu, Tianji Wu, Yi Shan, Yu Wang 0002, Yong He, Ningyi Xu, Huazhong Yang	Making Human Connectome Faster: GPU Acceleration of Brain Network Analysis.	ICPADS	2010	DBLP DOI BibTeX RDF
1	Paul Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang 0002	Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Yibo Chen, Yuan Xie, Yu Wang 0002, Andrés Takach	Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Yibo Chen, Yuan Xie, Yu Wang 0002, Andrés Takach	Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Jing Yan, Ning-Yi Xu, Xiongfei Cai, Rui Gao, Yu Wang 0002, Rong Luo, Feng-Hsiung Hsu	LambdaRank acceleration for relevance ranking in web search engines (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	lambdarank algorithms
1	Yi Shan, Bo Wang, Jing Yan, Yu Wang 0002, Ning-Yi Xu, Huazhong Yang	FPMR: MapReduce framework on FPGA.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA framework, RankBoost, MapReduce
1	Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang 0002, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan	New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components.	International Journal of Parallel Programming	2009	DBLP DOI BibTeX RDF
1	Hong Luo, Yu Wang 0002, Rong Luo, Huazhong Yang, Yuan Xie	Temperature-Aware NBTI Modeling Techniques in Digital Circuits.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Yuchun Ma, Xin Li, Yu Wang 0002, Xianlong Hong	Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Yu Wang 0002, Xukai Shen, Rong Luo, Huazhong Yang	Leakage Power Reduction through Dual Vth Assignment Considering Threshold voltage Variation.	Journal of Circuits, Systems, and Computers	2009	DBLP DOI BibTeX RDF
1	Yu Wang 0002, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, Huazhong Yang	On the efficacy of input Vector Control to mitigate NBTI effects and leakage power.	ISQED	2009	DBLP DOI BibTeX RDF
1	Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie, Yu Wang 0002	NBTI-aware statistical circuit delay assessment.	ISQED	2009	DBLP DOI BibTeX RDF
1	Jing Yan, Ning-Yi Xu, Xiongfei Cai, Rui Gao, Yu Wang 0002, Rong Luo, Feng-Hsiung Hsu	FPGA-based acceleration of neural network for ranking in web search engine with a streaming architecture.	FPL	2009	DBLP DOI BibTeX RDF
1	Xiaoming Chen, Yu Wang 0002, Yu Cao, Yuchun Ma, Huazhong Yang	Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.	ISLPED	2009	DBLP DOI BibTeX RDF	dynamic vdd scaling, leakage power, negative bias temperature instability (NBTI), dual vdd
1	Fubing Mao, Yuchun Ma, Ning Xu, Xianlong Hong, Yu Wang 0002	Multi-objective Floorplanning Based on Fuzzy Logic.	FSKD	2009	DBLP DOI BibTeX RDF
1	Yu Wang 0002, Jiang Xu, Shengxi Huang, Weichen Liu, Huazhong Yang	A case study of on-chip sensor network in multiprocessor system-on-chip.	CASES	2009	DBLP DOI BibTeX RDF	sensor network, reliability, low-power, system on chip, dynamic control, power grid noise
1	Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang 0002, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan	A framework for estimating NBTI degradation of microarchitectural components.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Yu Wang 0002, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang	Gate replacement techniques for simultaneous leakage and aging optimization.	DATE	2009	DBLP BibTeX RDF
1	Weichen Liu, Zonghua Gu, Jiang Xu, Yu Wang 0002, Mingxuan Yuan	An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	scheduling, optimization, model checking, memory management, synchronous dataflow
1	Yu Wang 0002, Ku He, Rong Luo, Hui Wang 0004, Huazhong Yang	Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Qian Ding, Yu Wang 0002, Hui Wang 0004, Rong Luo, Huazhong Yang	Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths.	ISQED	2008	DBLP DOI BibTeX RDF
1	Saihua Lin, Yu Wang 0002, Rong Luo, Huazhong Yang	A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Hong Luo, Yu Wang 0002, Ku He, Rong Luo, Huazhong Yang, Yuan Xie	Modeling of PMOS NBTI Effect Considering Temperature Variation.	ISQED	2007	DBLP DOI BibTeX RDF
1	Hong Luo, Yu Wang 0002, Ku He, Rong Luo, Huazhong Yang, Yuan Xie	A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect.	PATMOS	2007	DBLP DOI BibTeX RDF
1	Yu Wang 0002, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie	Temperature-aware NBTI modeling and the impact of input vector control on performance degradation.	DATE	2007	DBLP DOI BibTeX RDF
1	Ku He, Rong Luo, Yu Wang 0002	A power gating scheme for ground bounce reduction during mode transition.	ICCD	2007	DBLP DOI BibTeX RDF
1	Yu Wang 0002, Huazhong Yang, Hui Wang 0004	Signal-Path-Level Dual-VT Assignment for Leakage Power Reduction.	Journal of Circuits, Systems, and Computers	2006	DBLP DOI BibTeX RDF
1	Yu Wang 0002, Hai Lin, Huazhong Yang, Rong Luo, Hui Wang 0004	Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization.	ISQED	2006	DBLP DOI BibTeX RDF
1	Hai Lin, Yu Wang 0002, Rong Luo, Huazhong Yang, Hui Wang 0004	IR-drop Reduction Through Combinational Circuit Partitioning.	PATMOS	2006	DBLP DOI BibTeX RDF	Static Timing Analysis, IR-drop, circuit partitioning
1	Yu Wang 0002, Yongpan Liu, Rong Luo, Huazhong Yang, Hui Wang 0004	Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	leakage current reduction, two-phase fine-grain sleep transistor insertion, mixed integer linear programming
1	Yu Wang 0002, Yongpan Liu, Rong Luo, Huazhong Yang	Genetic Algorithm Based Fine-Grain Sleep Transistor Insertion Technique for Leakage Optimization.	ICNC	2006	DBLP DOI BibTeX RDF
1	Yu Wang 0002, Hui Wang 0004, Huazhong Yang	Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Yongpan Liu, Yu Wang 0002, Feng Zhang, Rong Luo, Hui Wang 0004	A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection.	APCCAS	2006	DBLP DOI BibTeX RDF

Publications of "Yu Wang 0002" ( http://dblp.L3S.de/Authors/Yu_Wang_0002 )