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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2 occurrences of 2 keywords
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Results
Found 7 publication records. Showing 7 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Tao Wang, Pei-Wen Luo, Yu-Shih Su, Liang-Chia Cheng, Ding-Ming Kwai, Yiyu Shi |
Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction.  |
ASP-DAC  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska |
Performance Optimization Using Variable-Latency Design Style. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu Shi, Shih-Chieh Chang |
Fault-tolerant 3D clock network. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang |
Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang |
Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. |
ICCAD |
2009 |
DBLP BibTeX RDF |
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| 1 | Yu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang |
Synthesis of a novel timing-error detection architecture. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
fault tolerance, Logic synthesis |
| 1 | Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska |
An Efficient Mechanism for Performance Optimization of Variable-Latency Designs. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
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