Search results for "Yuan Xie"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Guangyu Sun, Huazhong Yang, Yuan Xie	Performance/Thermal-Aware Design of 3D-Stacked L2 Caches for CMPs.	ACM Trans. Design Autom. Electr. Syst.	2012	DBLP DOI BibTeX RDF
1	Xiaoxia Wu, Wei Zhao, Mark Nakamoto, Chandra Nimmagadda, Durodami Lisk, Sam Gu, Riko Radojcic, Matt Nowak, Yuan Xie	Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Yuan Xie, Yanyun Qu, Cuihua Li, Wensheng Zhang	Online multiple instance gradient feature selection for robust visual tracking.	Pattern Recognition Letters	2012	DBLP DOI BibTeX RDF
1	Jing Xie, Vijaykrishnan Narayanan, Yuan Xie	Mitigating electromigration of power supply networks using bidirectional current stress.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Dimin Niu, Yang Xiao, Yuan Xie	Low power memristor-based ReRAM design with Error Correcting Code.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Jing Xie, Yu Wang, Yuan Xie	Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie	Thermal-aware power network design for IR drop reduction in 3D ICs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Guangyu Sun, Cong Xu, Yuan Xie	Modeling and design exploration of FBDRAM as on-chip memory.	DATE	2012	DBLP BibTeX RDF
1	Yibo Chen, Guangyu Sun, Qiaosha Zou, Yuan Xie	3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs.	DATE	2012	DBLP BibTeX RDF
1	Feng Wang 0004, Yuan Xie	Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model.	IEEE Trans. Dependable Sec. Comput.	2011	DBLP DOI BibTeX RDF
1	Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie	Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation.	IEEE Trans. Dependable Sec. Comput.	2011	DBLP DOI BibTeX RDF	temperature-aware NBTI modeling, circuit performance degradation, Negative bias temperature instability (NBTI), leakage reduction
1	Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi	Hybrid checkpointing using emerging nonvolatile memories for future exascale systems.	TACO	2011	DBLP DOI BibTeX RDF
1	Guangyu Sun, Yibo Chen, Xiangyu Dong, Jin Ouyang, Yuan Xie	Three-dimensional Integrated Circuits: Design, EDA, and Architecture.	Foundations and Trends in Electronic Design Automation	2011	DBLP DOI BibTeX RDF
1	Feng Wang 0004, Yibo Chen, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan	Variation-Aware Task and Communication Mapping for MPSoC Architecture.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Yuan Xie, Pol Marchal	Editorial- three-dimensional integrated circuits design.	IET Computers & Digital Techniques	2011	DBLP DOI BibTeX RDF
1	Xiangyu Dong, Xiaoxia Wu, Yuan Xie, Yiran Chen, Hai Helen Li	Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation.	IET Computers & Digital Techniques	2011	DBLP DOI BibTeX RDF
1	Yu Wang 0002, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang	Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Yuan Xie	Modeling, Architecture, and Applications for Emerging Memory Technologies.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF
1	Guangyu Sun, Christopher J. Hughes, Changkyu Kim, Jishen Zhao, Cong Xu, Yuan Xie, Yen-Kuang Chen	Moguls: a model to explore the memory hierarchy for bandwidth improvements.	ISCA	2011	DBLP DOI BibTeX RDF
1	Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das	Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs.	ISCA	2011	DBLP DOI BibTeX RDF
1	Han-Wei Chen, Suresh Srinivasan, Yuan Xie, Vijaykrishnan Narayanan	Impact of Circuit Degradation on FPGA Design Security.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Yibo Chen, Eren Kursun, Dave Motschman, Charles Johnson, Yuan Xie	Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs.	ISLPED	2011	DBLP BibTeX RDF
1	Vijaykrishnan Narayanan, Vinay Saripalli, Karthik Swaminathan, Ravindhiran Mukundrajan, Guangyu Sun, Yuan Xie, Suman Datta	Enabling architectural innovations using non-volatile memory.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	David Atienza, Yuan Xie, José L. Ayala, Ken S. Stevens (eds.)	Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011	ACM Great Lakes Symposium on VLSI	2011	DBLP BibTeX RDF
1	Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan	Automated mapping for reconfigurable single-electron transistor arrays.	DAC	2011	DBLP DOI BibTeX RDF
1	Jin Ouyang, Yuan Xie	Enabling quality-of-service in nanophotonic network-on-chip.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Wulong Liu, Yu Wang 0002, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang	On-chip hybrid power supply system for wireless sensor nodes.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Xiangyu Dong, Yuan Xie	AdaMS: Adaptive MLC/SLC phase-change memory design for file storage.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Guangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie	A frequent-value based PRAM memory architecture.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Jin Ouyang, Chuan Yang, Dimin Niu, Yuan Xie, Zhiwen Liu	F2BFLY: an on-chip free-space optical network with wavelength-switching.	ICS	2011	DBLP DOI BibTeX RDF
1	Jishen Zhao, Xiangyu Dong, Yuan Xie	An energy-efficient 3D CMP design with fine-grained voltage scaling.	DATE	2011	DBLP DOI BibTeX RDF
1	Cong Xu, Xiangyu Dong, Norman P. Jouppi, Yuan Xie	Design implications of memristor-based RRAM cross-point structures.	DATE	2011	DBLP DOI BibTeX RDF
1	Shekhar Srikantaiah, Emre Kultursay, Tao Zhang, Mahmut T. Kandemir, Mary Jane Irwin, Yuan Xie	MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy.	HPCA	2011	DBLP DOI BibTeX RDF
1	Jishen Zhao, Cong Xu, Yuan Xie	Bandwidth-aware reconfigurable cache design with hybrid memory technologies.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Cong Xu, Dimin Niu, Xiaochun Zhu, Seung H. Kang, Matt Nowak, Yuan Xie	Device-architecture co-optimization of STT-RAM based memory for low power embedded systems.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Guangyu Sun, Eren Kursun, Jude A. Rivers, Yuan Xie	Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory.	ICCD	2011	DBLP DOI BibTeX RDF
1	Jue Wang, Xiangyu Dong, Guangyu Sun, Dimin Niu, Yuan Xie	Energy-efficient multi-level cell phase-change memory system with data encoding.	ICCD	2011	DBLP DOI BibTeX RDF
1	Qiaosha Zou, Yibo Chen, Yuan Xie, Alan Su	System-level design space exploration for three-dimensional (3D) SoCs.	CODES+ISSS	2011	DBLP DOI BibTeX RDF
1	Xiaoxia Wu, Jian Li, Lixin Zhang 0002, Evan Speight, Ramakrishnan Rajamony, Yuan Xie	Design exploration of hybrid caches with disparate memory technologies.	TACO	2010	DBLP DOI BibTeX RDF
1	Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie	Test-access mechanism optimization for core-based three-dimensional SOCs.	Microelectronics Journal	2010	DBLP DOI BibTeX RDF
1	Gabriel H. Loh, Yuan Xie	3D Stacked Microprocessor: Are We There Yet?	IEEE Micro	2010	DBLP DOI BibTeX RDF
1	Xiangyu Dong, Jishen Zhao, Yuan Xie	Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy	Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Total Power Optimization for Combinational Logic Using Genetic Algorithms.	Signal Processing Systems	2010	DBLP DOI BibTeX RDF
1	Li Jiang, Yuxi Liu, Lian Duan, Yuan Xie, Qiang Xu	Modeling TSV open defects in 3D-stacked DRAM.	ITC	2010	DBLP DOI BibTeX RDF
1	Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi	Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support.	SC	2010	DBLP DOI BibTeX RDF
1	Dimin Niu, Yiran Chen, Yuan Xie	Low-power dual-element memristor based memory design.	ISLPED	2010	DBLP DOI BibTeX RDF	memristor, low power, nonvolatile memory
1	Yibo Chen, Jishen Zhao, Yuan Xie	3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory.	ISLPED	2010	DBLP DOI BibTeX RDF	non-volatile FPGA, phase-change memory, 3D IC
1	Tao Zhang, Kui Wang, Yi Feng, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin	A customized design of DRAM controller for on-chip 3D DRAM stacking.	CICC	2010	DBLP DOI BibTeX RDF
1	Jin Ouyang, Yuan Xie	LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support.	MICRO	2010	DBLP DOI BibTeX RDF
1	Jishen Zhao, Xiangyu Dong, Yuan Xie	Cost-aware three-dimensional (3D) many-core multiprocessor design.	DAC	2010	DBLP DOI BibTeX RDF	3D IC design, many-core processor design, cost modeling
1	Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie	Impact of process variations on emerging memristor.	DAC	2010	DBLP DOI BibTeX RDF	memristor, process variation, nonvolatile memory
1	Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li	Cost-driven 3D integration with interconnect layers.	DAC	2010	DBLP DOI BibTeX RDF	interconnect service layer, three-dimensional integrated circuit, network-on-chip
1	Paul Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang 0002	Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Yibo Chen, Yuan Xie, Yu Wang 0002, Andrés Takach	Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie	Energy and performance driven circuit design for emerging phase-change memory.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Yibo Chen, Yuan Xie, Yu Wang 0002, Andrés Takach	Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Yuan Xie	Processor Architecture Design Using 3D Integration Technology.	VLSI Design	2010	DBLP DOI BibTeX RDF	3D Technology, Architeture
1	Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun, Naehyuck Chang, Yuan Xie	Energy- and endurance-aware design of phase change memory caches.	DATE	2010	DBLP BibTeX RDF
1	Jing Xie, Xiangyu Dong, Yuan Xie	3D memory stacking for fast checkpointing/restore applications.	3DIC	2010	DBLP DOI BibTeX RDF
1	Tao Zhang, Kui Wang, Yi Feng 0003, Yan Chen, Qun Li, Bing Shao, Jing Xie, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin	A 3D SoC design for H.264 application with on-chip DRAM stacking.	3DIC	2010	DBLP DOI BibTeX RDF
1	Guangyu Sun, Yongsoo Joo, Yibo Chen, Dimin Niu, Yuan Xie, Yiran Chen, Hai Li	A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.	HPCA	2010	DBLP DOI BibTeX RDF
1	Yibo Chen, Dimin Niu, Yuan Xie, Krishnendu Chakrabarty	Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Jin Ouyang, Jing Xie, Matthew Poremba, Yuan Xie	Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Rajaraman Ramanarayanan, Vijay Degalahal, Krishnan Ramakrishnan, Jungsub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu	Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits.	IEEE Trans. Dependable Sec. Comput.	2009	DBLP DOI BibTeX RDF
1	Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang 0002, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan	New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components.	International Journal of Parallel Programming	2009	DBLP DOI BibTeX RDF
1	Hong Luo, Yu Wang 0002, Rong Luo, Huazhong Yang, Yuan Xie	Temperature-Aware NBTI Modeling Techniques in Digital Circuits.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Madhu Mutyam, Feng Wang 0004, Krishnan Ramakrishnan, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin	Process-Variation-Aware Adaptive Cache Architecture and Management.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
1	Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie	Scan-chain design and optimization for three-dimensional integrated circuits.	JETC	2009	DBLP DOI BibTeX RDF	scan-chain design, genetic algorithm, integer linear programming, randomized rounding, LP relaxation, 3D ICs
1	David S. Kung, Yuan Xie	Guest Editors' Introduction: Opportunities and Challenges of 3D Integration.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Yuan Xie, Yibo Chen	Statistical High-Level Synthesis under Process Variability.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Yu Wang 0002, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, Huazhong Yang	On the efficacy of input Vector Control to mitigate NBTI effects and leakage power.	ISQED	2009	DBLP DOI BibTeX RDF
1	Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie, Yu Wang 0002	NBTI-aware statistical circuit delay assessment.	ISQED	2009	DBLP DOI BibTeX RDF
1	Xiaoxia Wu, Jian Li, Lixin Zhang 0002, Evan Speight, Ramakrishnan Rajamony, Yuan Xie	Hybrid cache architecture with disparate memory technologies.	ISCA	2009	DBLP DOI BibTeX RDF	hybrid cache architecture, three-dimensional ic
1	Xiangyu Dong, Naveen Muralimanohar, Norman P. Jouppi, Richard Kaufmann, Yuan Xie	Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems.	SC	2009	DBLP DOI BibTeX RDF
1	Guangyu Sun, Xiaoxia Wu, Yuan Xie	Exploration of 3D stacked L2 cache design for high performance and efficient thermal control.	ISLPED	2009	DBLP DOI BibTeX RDF	thermal control, performance, 3D, L2 caches
1	Norman P. Jouppi, Yuan Xie	Emerging technologies and their impact on system design.	ISLPED	2009	DBLP DOI BibTeX RDF	new non-volatile memory technology, emerging technology, 3d integration
1	Luca P. Carloni, Partha Pande, Yuan Xie	Networks-on-chip in emerging interconnect paradigms: Advantages and challenges.	NOCS	2009	DBLP DOI BibTeX RDF
1	Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Tao Zhang, Yuan Xie, Frank Mueller	CheckerCore: enhancing an FPGA soft core to capture worst-case execution times.	CASES	2009	DBLP DOI BibTeX RDF	LEON3, checkercore, shadow pipeline, FPGA, embedded system, real-time, WCET, worst-case-execution-time, SPARC
1	Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang 0002, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan	A framework for estimating NBTI degradation of microarchitectural components.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Srinath Sridharan, Michael DeBole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan	A criticality-driven microarchitectural three dimensional (3D) floorplanner.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Yibo Chen, Yuan Xie	Tolerating process variations in high-level synthesis using transparent latches.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Xiangyu Dong, Yuan Xie	System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs).	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Feng Wang 0004, Yuan Xie, Andrés Takach	Variation-aware resource sharing and binding in behavioral synthesis.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Yu Wang 0002, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang	Gate replacement techniques for simultaneous leakage and aging optimization.	DATE	2009	DBLP BibTeX RDF
1	Xiaoxia Wu, Jian Li, Lixin Zhang 0002, Evan Speight, Yuan Xie	Power and performance of read-write aware Hybrid Caches with non-volatile memories.	DATE	2009	DBLP BibTeX RDF
1	Brent Hollosi, Tao Zhang, Ravi Sankar Parameswaran Nair, Yuan Xie, Jia Di, Scott C. Smith	Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs.	3DIC	2009	DBLP DOI BibTeX RDF
1	Jin Ouyang, Guangyu Sun, Yibo Chen, Lian Duan, Tao Zhang, Yuan Xie, Mary Jane Irwin	Arithmetic unit design using 180nm TSV-based 3D stacking technology.	3DIC	2009	DBLP DOI BibTeX RDF
1	Yaoyao Ye, Lian Duan, Jiang Xu, Jin Ouyang, Mo Kwai Hung, Yuan Xie	3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC).	3DIC	2009	DBLP DOI BibTeX RDF
1	Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen	A novel architecture of the 3D stacked MRAM L2 cache for CMPs.	HPCA	2009	DBLP DOI BibTeX RDF
1	Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie	Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning.	ICCAD	2009	DBLP BibTeX RDF
1	Xiangyu Dong, Norman P. Jouppi, Yuan Xie	PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM.	ICCAD	2009	DBLP BibTeX RDF
1	Ahmed Al-Maashri, Guangyu Sun, Xiangyu Dong, Vijay Narayanan, Yuan Xie	3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis.	ICCD	2009	DBLP DOI BibTeX RDF
1	Brandon Noia, Krishnendu Chakrabarty, Yuan Xie	Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs.	ICCD	2009	DBLP DOI BibTeX RDF
1	Suresh Srinivasan, Krishnan Ramakrishnan, Prasanth Mangalagiri, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin, Karthik Sarpatwari	Toward Increasing FPGA Lifetime.	IEEE Trans. Dependable Sec. Comput.	2008	DBLP DOI BibTeX RDF	Reliability, Reconfigurable hardware, availability and serviceability
1	Yuan Xie, Jason Cong, Paul D. Franzon	Editorial: Special issue on 3D integrated circuits and microarchitectures.	JETC	2008	DBLP DOI BibTeX RDF
1	Yuh-Fang Tsai, Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin	Design Space Exploration for 3-D Cache.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Shengqi Yang, Wenping Wang, Tiehan Lv, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie	Case Study of Reliability-Aware and Low-Power Design.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, Kenan Unlu	Hierarchical Soft Error Estimation Tool (HSEET).	ISQED	2008	DBLP DOI BibTeX RDF	Reliability, Soft Errors, Flip-Flop, Combinational Logic
1	Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie	Test-Access Solutions for Three-Dimensional SOCs.	ITC	2008	DBLP DOI BibTeX RDF

Publications of "Yuan Xie" ( http://dblp.L3S.de/Authors/Yuan_Xie )