Search results for "Yuchun Ma"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Kan Wang, Sheqin Dong, Yuchun Ma, Satoshi Goto, Jason Cong	Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs.	ISQED	2012	DBLP DOI BibTeX RDF
1	Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie	Thermal-aware power network design for IR drop reduction in 3D ICs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang, Jinian Bian	PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs.	ARC	2012	DBLP DOI BibTeX RDF
1	Kan Wang, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong	Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Tao Lin, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, Satoshi Goto	Novel and efficient min cut based voltage assignment in gate level.	ISQED	2011	DBLP DOI BibTeX RDF
1	Hong Luo, Xiaoming Chen, Jyothi Velamala, Yu Wang, Yu Cao, Vikas Chandra, Yuchun Ma, Huazhong Yang	Circuit-level delay modeling considering both TDDB and NBTI.	ISQED	2011	DBLP DOI BibTeX RDF
1	Wulong Liu, Yu Wang 0002, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang	On-chip hybrid power supply system for wireless sensor nodes.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto	Network flow-based simultaneous retiming and slack budgeting for low power design.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong	Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Binjie Song, Shan Zeng, Yuchun Ma, Ning Xu, Yu Wang	Tree-Based Partitioning Approach for Network-on-Chip Synthesis.	CAD/Graphics	2011	DBLP DOI BibTeX RDF
1	Yuchun Ma, Qiang Zhou, Pingqiang Zhou, Xianlong Hong	Thermal Impacts of Leakage Power in 2D/3D floorplanning.	Journal of Circuits, Systems, and Computers	2010	DBLP DOI BibTeX RDF
1	Xu He, Sheqin Dong, Yuchun Ma	Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs.	Integration	2010	DBLP DOI BibTeX RDF
1	Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong	PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang	Simultaneous slack budgeting and retiming for synchronous circuits optimization.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Yuchun Ma, Xin Li, Yu Wang 0002, Xianlong Hong	Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong	Simultaneous buffer and interlayer via planning for 3D floorplanning.	ISQED	2009	DBLP DOI BibTeX RDF
1	Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong	Incremental power optimization for multiple supply voltage design.	ISQED	2009	DBLP DOI BibTeX RDF
1	Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong	Modern Floorplanning with Boundary Clustering Constraint.	ISVLSI	2009	DBLP DOI BibTeX RDF
1	Xiaoming Chen, Yu Wang 0002, Yu Cao, Yuchun Ma, Huazhong Yang	Variation-aware supply voltage assignment for minimizing circuit degradation and leakage.	ISLPED	2009	DBLP DOI BibTeX RDF	dynamic vdd scaling, leakage power, negative bias temperature instability (NBTI), dual vdd
1	Fubing Mao, Yuchun Ma, Ning Xu, Xianlong Hong, Yu Wang 0002	Multi-objective Floorplanning Based on Fuzzy Logic.	FSKD	2009	DBLP DOI BibTeX RDF
1	Xin Li, Yuchun Ma, Xianlong Hong	A novel thermal optimization flow using incremental floorplanning for 3D ICs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, Jason Cong	Investigating the effects of fine-grain three-dimensional integration on microarchitecture design.	JETC	2008	DBLP DOI BibTeX RDF	3D packing, microarchitecture, 3D integration, thermal
1	Xiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong	IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization.	ISQED	2008	DBLP DOI BibTeX RDF	interconnect power, piecewise model, slack
1	Jiemin Liu, Yuchun Ma, Yuan Gao	MRAPF: Minimum RTT Asymmetric-Path First for Mobile Multi-homed End-to-End Transfer.	FSKD	2008	DBLP DOI BibTeX RDF
1	Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong	LP based white space redistribution for thermal via planning and performance optimization in 3D ICs.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong	Interconnect Power Optimization Based on Timing Analysis.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong	An effective buffer planning algorithm for IP based fixed-outline SOC placement.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	buffer planning, very large scale integration (VLSI), floorplanning, fixed-outline
1	Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma	An accurate and efficient probabilistic congestion estimation model in x architecture.	SLIP	2007	DBLP DOI BibTeX RDF	congestion estimation, dynamic resource assignment, the X architecture, routability
1	Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou	Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.	ASP-DAC	2007	DBLP DOI BibTeX RDF	graph-based approach, microarchitecture pipelining optimization, throughput-aware floorplanning, block pipelining, interconnect pipelining, graph-based algorithm, mixed integer linear programming, wire pipelining
1	Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong	Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation.	ASP-DAC	2007	DBLP DOI BibTeX RDF	thermal-optimal placement, thermal-driven symmetry constraint, analog layout, thermal constraint, hot-spot effect, temperature gradient, symmetrical devices, placement process, geometric symmetry, corner block list, thermal model
1	Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma	A Fast 3D-BSG Algorithm for 3D Packing Problem.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Pingqiang Zhou, Yuchun Ma, Qiang Zhou, Xianlong Hong	Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning.	CAD/Graphics	2007	DBLP DOI BibTeX RDF
1	Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou	3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, Jason Cong	Fine grain 3D integration for microarchitecture design through cube packing exploration.	ICCD	2007	DBLP DOI BibTeX RDF
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu	General Floorplans with L/T-Shaped Blocks Using Corner Block List.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	corner block list, L/T-shaped blocks, floorplanning
1	Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang	An automated design flow for 3D microarchitecture evaluation.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma	A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu	Buffer planning as an Integral part of floorplanning with consideration of routing congestion.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng	Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.	ISQED	2005	DBLP DOI BibTeX RDF
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng	Buffer Planning Algorithm Based on Partial Clustered Floorplanning.	ISQED	2005	DBLP DOI BibTeX RDF
1	Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng	VLSI block placement with alignment constraints based on corner block list.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng	Performance constrained floorplanning based on partial clustering [IC layout].	ISCAS	2005	DBLP DOI BibTeX RDF
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu	Stairway compaction using corner block list and its applications with rectilinear blocks.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	corner block list, rectilinear blocks, Floorplanning
1	Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu	A buffer planning algorithm for chip-level floorplanning.	Science in China Series F: Information Sciences	2004	DBLP DOI BibTeX RDF
1	Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu	Corner block list representation and its application with boundary constraints.	Science in China Series F: Information Sciences	2004	DBLP DOI BibTeX RDF
1	Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu	Fast Evaluation of Bounded Slice-Line Grid.	J. Comput. Sci. Technol.	2004	DBLP DOI BibTeX RDF
1	Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu	A buffer planning algorithm with congestion optimization.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu	Buffer allocation algorithm with consideration of routing congestion.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu	An integrated floorplanning with an efficient buffer planning algorithm.	ISPD	2003	DBLP DOI BibTeX RDF	floorplanning, buffer insertion, routability
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu	Dynamic global buffer planning optimization based on detail block locating and congestion analysis.	DAC	2003	DBLP DOI BibTeX RDF	congestion, floorplanning, buffer insertion, routability
1	Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu	Evaluating a bounded slice-line grid assignment in O(nlogn) time.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu	Arbitrary convex and concave rectilinear block packing based on corner block list.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu	Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks.	VLSI Design	2002	DBLP DOI BibTeX RDF
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu	Floorplanning with abutment constraints based on corner block list.	Integration	2001	DBLP DOI BibTeX RDF
1	Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu	Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List.	DAC	2001	DBLP DOI BibTeX RDF
1	Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu	VLSI floorplanning with boundary constraints based on corner block list.	ASP-DAC	2001	DBLP DOI BibTeX RDF

Publications of "Yuchun Ma" ( http://dblp.L3S.de/Authors/Yuchun_Ma )