Search    Browse

The FacetedDBLP logo    Search for: in:

Disable automatic phrases ?     Syntactic query expansion: ?

Publications of "Yuji Osaki" ( http://dblp.L3S.de/Authors/Yuji_Osaki )

  Author page on DBLP  Author page in RDF  Community of Yuji Osaki in ASPL-2

Publication years (Num. hits)
2011 (4)
Publication types (Num. hits)
article(2) inproceedings(2)
Venues (Conferences, Journals, ...)
IEICE Transactions(2) ASP-DAC(1) ESSCIRC(1)
Authors
Masahiro Numa(4) Nobutaka Kuroki(4) Tetsuya Hirose(4) Yuji Osaki(4) Kei Matsumoto(2)
GrowBag graphs for keyword ? (Num. hits/coverage)

Group by:
No Growbag Graphs found.
Results
Found 4 publication records. Showing 4 according to the selection in the facets
Hits ?▲ Authors Title Venue Year Link Author keywords
1Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique. Search on Bibsonomy IEICE Transactions The full citation details ... 2011 DBLP  BibTeX  RDF
1Kei Matsumoto, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit. Search on Bibsonomy IEICE Transactions The full citation details ... 2011 DBLP  BibTeX  RDF
1Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs. Search on Bibsonomy ESSCIRC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder. Search on Bibsonomy ASP-DAC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
Displaying result #1 - #4 of 4 (100 per page; Change: )
Valid XHTML 1.1! Valid CSS! [Valid RSS]
Maintained by Jörg Diederich.
Based upon DBLP by Michael Ley.