Search results for "Yukio Mitsuyama"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye	Stress Probability Computation for Estimating NBTI-Induced Delay Degradation.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye	Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures.	FPL	2011	DBLP DOI BibTeX RDF
1	Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye	NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode.	PATMOS	2011	DBLP DOI BibTeX RDF
1	Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye	Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye	Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution.	ISQED	2010	DBLP DOI BibTeX RDF
1	Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye	Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration.	ISQED	2010	DBLP DOI BibTeX RDF
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Takehiko Amaki, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling.	WISA	2010	DBLP DOI BibTeX RDF
1	Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Dawood Alnajiar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi, Takao Onoye	Coarse-grained dynamically reconfigurable architecture with flexible reliability.	FPL	2009	DBLP DOI BibTeX RDF
1	Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	body bias clustering, performance compensation, layout, manufacturing variability, subthreshold circuits
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits.	CICC	2009	DBLP DOI BibTeX RDF
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Yukio Mitsuyama, Kazuma Takahashi, Rintaro Imai, Masanori Hashimoto, Takao Onoye, Isao Shirakawa	Area-Efficient Reconfigurable Architecture for Media Processing.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	layout, body bias
1	Yukio Mitsuyama, Motoki Kimura, Takao Onoye, Isao Shirakawa	Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa	A dynamically reconfigurable hardware-based cipher chip.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa	VLSI architecture of dynamically reconfigurable hardware-based cipher.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Koji Asari, Yukio Mitsuyama, Takao Onoye, Isao Shirakawa, Hiroshige Hirano, Toshiyuki Honda, Tatsuo Otsuki, Takaaki Baba, Teresa H. Y. Meng	FeRAM Circuit Technology for System on a Chip.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF

Publications of "Yukio Mitsuyama" ( http://dblp.L3S.de/Authors/Yukio_Mitsuyama )