| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Gilbert Kowarzyk, N. Blanger, David Haccoun, Yvon Savaria |
Efficient Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes.  |
IEEE Transactions on Communications  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre |
Loop Acceleration Exploration for ASIP Architecture. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Afshin Nourivand, Asim J. Al-Khalili, Yvon Savaria |
Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Zaid Al-bayati, Otmane Aït Mohamed, Syed Rafay Hasan, Yvon Savaria |
A novel hybrid FIFO asynchronous clock domain crossing interfacing method. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Omar Al-Terkawi Hasib, Mohamad Sawan, Yvon Savaria |
A Low-Power Asynchronous Step-Down DC-DC Converter for Implantable Devices. |
IEEE Trans. Biomed. Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rahul Singh, Yves Audet, Yves Gagnon, Yvon Savaria, Étienne Boulais, Michel Meunier |
A Laser-Trimmed Rail-to-Rail Precision CMOS Operational Amplifier. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Afshin Nourivand, Asim J. Al-Khalili, Yvon Savaria |
Analysis of Resistive Open Defects in Drowsy SRAM Cells. |
J. Electronic Testing |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad |
All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria |
Repeater insertion in power-managed VLSI systems. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Diana Carolina Gil, Rana Farah, J. M. Pierre Langlois, Guillaume-Alexandre Bilodeau, Yvon Savaria |
Comparative analysis of contrast enhancement algorithms in surveillance imaging. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Zarrabi, A. J. Al-Khalili, Yvon Savaria |
Activity management in battery-powered embedded systems: A case study of ZigBee® WSN. |
ICECS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shervin Vakili, Diana Carolina Gil, J. M. Pierre Langlois, Yvon Savaria, Guy Bois |
Customized embedded processor design for global photographic tone mapping. |
ICECS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Gilbert Kowarzyk, Normand Bélanger, Yvon Savaria |
A GPGPU-based software implementation of the PBDI deinterlacing algorithm. |
ICECS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ghaith Bany Hamad, Otmane Aït Mohamed, Syed Rafay Hasan, Yvon Savaria |
SEGP-Finder: Tool for identification of Soft Error Glitch-Propagating paths at gate level. |
ICECS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rana Farah, Qifeng Gan, J. M. Pierre Langlois, Guillaume-Alexandre Bilodeau, Yvon Savaria |
A tracking algorithm suitable for embedded systems implementation. |
ICECS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad |
Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | David Marche, Yvon Savaria |
Modeling R-2R Segmented-Ladder DACs. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad |
Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria |
An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Omar Al-Terkawi Hasib, Mohamad Sawan, Yvon Savaria |
Fully integrated ultra-low-power asynchronously driven step-down DC-DC converter. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed Bougataya, Oussama Berriah, Ahmed Lakhssassi, Adel-Omar Dahmane, Yves Blaquière, Yvon Savaria, Richard Norman, Richard Prytula |
Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit. |
ICECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Olivier Valorge, Yves Blaquière, Yvon Savaria |
A spatially reconfigurable fast differential interface for a wafer scale configurable platform. |
ICECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Louis-Francois Tanguay, Mohamad Sawan, Yvon Savaria |
A very-high output impedance charge pump for low-voltage low-power PLLs. |
Microelectronics Journal |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Saeid Hashemi, Mohamad Sawan, Yvon Savaria |
A novel low-drop CMOS active rectifier for RF-powered devices: Experimental results. |
Microelectronics Journal |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Patrick Mahoney, Yvon Savaria, Guy Bois, Patrice Plante |
Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories. |
T. HiPEAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois |
High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse. |
Signal Processing Systems |
2009 |
DBLP DOI BibTeX RDF |
ASIP, Acceleration, Video processing, Data reuse |
| 1 | David Marche, Yvon Savaria, Yves Gagnon |
An Improved Switch Compensation Technique for Inverted R-2R Ladder DACs. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Naderi, Mohamad Sawan, Yvon Savaria |
A low-power 2GHz data conversion using delta modulation for portable application. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria |
An interconnect-aware delay model for dynamic voltage scaling in NM technologies. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
dynamic voltage scaling (dvs), interconnects, delay model |
| 1 | Etienne Lepercq, Yves Blaquière, Richard Norman, Yvon Savaria |
Workflow for an Electronic Configurable Prototyping System. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Syed Rafay Hasan, Bill Pontikakis, Yvon Savaria |
An All-digital Skew-adaptive Clock Scheduling Algorithm for Heterogeneous Multiprocessor Systems on Chips (MPSoCs). |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria |
Estimation of energy performance in computing platforms. |
ICECS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Saeid Hashemi, Mohamad Sawan, Yvon Savaria |
A low-area power-efficient CMOS active rectifier for wirelessly powered medical devices. |
ICECS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Max-Elie Salomon, Badre Izouggaghen, Abdelhakim Khouas, Yvon Savaria |
Spur Model for a Fixed-Frequency Signal Subject to Periodic Jitter. |
IEEE T. Instrumentation and Measurement |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Wayne Luk, Yvon Savaria, Oskar Mencer |
Guest Editorial: 20 Years of ASAP. |
Signal Processing Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Naderi, Mohamad Sawan, Yvon Savaria |
On the Design of Undersampling Continuous-Time Bandpass Delta-Sigma Modulators for Gigahertz Frequency A/D Conversion. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hung Tien Bui, Yvon Savaria |
Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-GHz Frequency-Locked Loop. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | David Marche, Yvon Savaria, Yves Gagnon |
Laser Fine-Tuneable Deep-Submicrometer CMOS 14-bit DAC. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre |
Loop-oriented metrics for exploring an application-specific architecture design-space. |
ASAP |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Amine Anane, El Mostapha Aboulhamid, Julie Vachon, Yvon Savaria |
Modeling and simulation of complex heterogeneous systems. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre |
A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration. |
VLSI Signal Processing |
2007 |
DBLP DOI BibTeX RDF |
data grouping and reuse, optimization, parallelism, application-specific instruction-set processor, design exploration |
| 1 | N. Gorse, P. Bélanger, Alexandre Chureau, El Mostapha Aboulhamid, Yvon Savaria |
A high-level requirements engineering methodology for electronic system-level design. |
Computers & Electrical Engineering |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Vincent Binet, Yvon Savaria, Michel Meunier, Yves Gagnon |
Modeling the Substrate Noise Injected by a DC-DC Converter. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Rahul Singh, Yves Audet, Yves Gagnon, Yvon Savaria |
Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Bill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria |
A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Syed Rafay Hasan, Yvon Savaria |
Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Chebli, Mohamad Sawan, Yvon Savaria, Kamal El-Sankary |
High-Voltage DMOS Integrated Circuits with Floating Gate Protection Technique. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Marc-André Cantin, Yvon Savaria, D. Prodanos, Pierre Lavoie |
A Metric for Automatic Word-Length Determination of Hardware Datapaths. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois |
Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor. |
SiPS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Abdelaziz Ammari, Régis Leveugle, B. Nicolescu, Yvon Savaria |
Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection. |
DELTA |
2006 |
DBLP DOI BibTeX RDF |
software hardening, fault detection, fault injection, dependability evaluation |
| 1 | Hung Tien Bui, Yvon Savaria |
High speed differential pulse-width control loop based on frequency-to-voltage converters. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
PWCL, frequency-to-voltage, high-speed, duty cycle |
| 1 | Ali Naderi, Mohamad Sawan, Yvon Savaria |
Design of an Active-RC Bandpass Filter for a Subsampling RF Delta Modulator. |
CCECE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | N. Ignat, B. Nicolescu, Yvon Savaria, Gabriela Nicolescu |
Soft-error classification and impact analysis on real-time operating systems. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Z. Huang, Yvon Savaria, Mohamad Sawan, R. Meinga |
High-voltage operational amplifier based on dual floating-gate transistors. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ami Castonguay, Yvon Savaria |
Architecture of a hypertransport tunnel. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Maria Mbaye, D. Lebel, Normand Bélanger, Yvon Savaria, Samuel Pierre |
Design exploration with an application-specific instruction-set processor for ELA deinterlacing. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ali Naderi, Mohamad Sawan, Yvon Savaria |
A novel 2-GHz band-pass delta modulator dedicated to wireless receivers. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Zarrabi, Haydar Saaied, Asim J. Al-Khalili, Yvon Savaria |
Zero skew differential clock distribution network. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Saeid Hashemi, Mohamad Sawan, Yvon Savaria |
A power planning model for implantable stimulators. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Bill Pontikakis, François R. Boyer, Yvon Savaria |
A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria |
Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques. |
ACM Trans. Design Autom. Electr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
multiphase, sequential circuit, software pipelining, clock, Retiming |
| 1 | Hakim Khali, Yvon Savaria, Jean-Louis Houle |
A system level implementation strategy and partitioning heuristic for LUT-based applications. |
Computers & Electrical Engineering |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Ling, Yvon Savaria |
Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ami Castonguay, Yvon Savaria |
A HyperTransport Chip-to-Chip Interconnect Tunnel Developed Using SystemC. |
IEEE International Workshop on Rapid System Prototyping |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Bill Pontikakis, François R. Boyer, Yvon Savaria |
Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. |
IWSOC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Grou-Szabo, Hany Ghattas, Yvon Savaria, Gabriela Nicolescu |
Component-Based Methodology for Hardware Design of a Dataflow Processing Network. |
IWSOC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Hung Tien Bui, Yvon Savaria |
A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs. |
IWSOC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexandre Chureau, Yvon Savaria, El Mostapha Aboulhamid |
The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | H. G. Epassa, François R. Boyer, Yvon Savaria |
Implementation of a cycle by cycle variable speed processor. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | A. Landry, Mohamed Nekili, Yvon Savaria |
A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | G. Provost, Marc-André Cantin, Mohamad Sawan, Christian Cardinal, Yvon Savaria, David Haccoun |
Fast parameters optimization of an iterative decoder using a configurable hardware accelerator. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Dinh Hung Dang, Yvon Savaria, Mohamad Sawan |
A novel approach for implementing ultra-high speed flash ADC using MCML circuits. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | G. Wild, Yvon Savaria, Michel Meunier |
Characterization of laser-induced photoexcitation effect on a surrounding CMOS ring oscillator. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Catudal, Marc-André Cantin, Yvon Savaria |
Parameters estimation applied to automatic video processing algorithms validation. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Max-Elie Salomon, Abdelhakim Khouas, Yvon Savaria |
A complete spurs distribution model for direct digital period synthesizers. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | David Marche, Yves Gagnon, Yvon Savaria |
. A new switch compensation technique for inverted R-2R ladder DACs. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Simon Rioux, Alain Lacourse, Yvon Savaria, Michel Meunier |
Design methods for CMOS low-current finely tunable voltage references covering a wide output range. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre |
Application specific instruction-set processor generation for video processing based on loop optimization. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Marc-André Cantin, S. Regimbal, S. Catudal, Yvon Savaria |
A Unified Environment to Assess Image Quality in Video Processing. |
Journal of Circuits, Systems, and Computers |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed Layachi, Yvon Savaria, Alain Rochefort |
The Effect of p-Coupling on the Electronic Properties of 1, 4-Dithiol Benzene Stacking. |
ICMENS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Olivier Duval, L.-P. Lafrance, Yvon Savaria, Pierre Desjardins |
An Integrated Test Platform for Nanostructure Electrical Characterization. |
ICMENS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexandre Chureau, Yvon Savaria, El Mostapha Aboulhamid |
Interface-based Design of Systems-on-Chip using UML-RT. |
IWSOC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Pascal Nsame, Yvon Savaria |
A Customizable Embedded SoC Platform Architecture. |
IWSOC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | L.-P. Lafrance, Yvon Savaria |
A Framework for Implementing Reusable Digital Signal Processing Modules. |
IWSOC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Regimbal, Yvon Savaria, Guy Bois |
Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models. |
IWSOC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Hung Tien Bui, Yvon Savaria |
10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS. |
IWSOC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | D. Morin, F. Normandin, M.-E. Grandmaison, H. Dang, Yvon Savaria, Mohamad Sawan |
An Intellectual Property Module for Auto-Calibration of Time-Interleaved Pipelined Analog-to-Digital Converters. |
IWSOC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Kevin Peterson, Yvon Savaria |
Assertion-based on-line verification and debug environment for complex hardware systems. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Badre Izouggaghen, Abdelhakim Khouas, Yvon Savaria |
Spurs modeling in direct digital period synthesizers related to phase accumulator truncation. |
ISCAS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Olivier Duval, Yvon Savaria |
An on-chip delay measurements module for nanostructures characterization. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Dorin Emil Calbaza, Ioan Cordos, Nigel Seth-Smith, Yvon Savaria |
An ADPLL circuit using a DDPS for genlock applications. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Hung Tien Bui, Yvon Savaria |
Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | B. Nicolescu, Yvon Savaria, Raoul Velazco |
Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique. |
IOLTS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric Granger, Yvon Savaria, Pierre Lavoie |
A Pattern Reordering Approach Based on Ambiguity Detection for Online Category Learning. |
IEEE Trans. Pattern Anal. Mach. Intell. |
2003 |
DBLP DOI BibTeX RDF |
online category learning, pattern recognition, Ambiguity, partitional clustering, reject option |
| 1 | Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria |
Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Hakim Khali, Yvon Savaria, Jean-Louis Houle, Marc Rioux, J.-Angelo Beraldin, D. Poussart |
Improvement of sensor accuracy in the case of a variable surface reflectance gradient for active laser range finders. |
IEEE T. Instrumentation and Measurement |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria |
Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
supply voltage scaling, performance, power consumption, CMOS, retiming, digital design |
| 1 | S. Regimbal, Jean-Francois Lemire, Yvon Savaria, Guy Bois, El Mostapha Aboulhamid, A. Baron |
Automating Functional Coverage Analysis Based on an Executable Specification. |
IWSOC |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Mathieu Renaud, Yvon Savaria |
A CMOS three-state frequency detector complementary to an enhanced linear phase detector for PLL, DLL or high frequency clock skew measurement. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Yiyan Tang, Lie Qian, Yuke Wang, Yvon Savaria |
A new memory reference reduction method for FFT implementation on DSP. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
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