Search results for "Zainalabedin Navabi"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Atieh Lotfi, Parisa Kabiri, Zainalabedin Navabi	Configurable architecture for memory BIST.	EWDTS	2011	DBLP DOI BibTeX RDF
1	Nastaran Nemati, Zainalabedin Navabi	Adaptation of Standard RT Level BIST Architectures for System Level Communication Testing.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	B. Khodabandeloo, S. A. Hoseini, S. Taheri, M. H. Haghbayan, M. R. Babaei, Zainalabedin Navabi	Online Test Macro Scheduling and Assignment in MPSoC Design.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Fatemeh Javaheri, Majid Namaki-Shoushtari, Parastoo Kamranfar, Zainalabedin Navabi	Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, Zainalabedin Navabi	EDXY - A low cost congestion-aware routing algorithm for network-on-chips.	Journal of Systems Architecture - Embedded Systems Design	2010	DBLP DOI BibTeX RDF
1	M. R. Jamali, Masood Deh-Yadegari, Arash Arami, Caro Lucas, Zainalabedin Navabi	Real-time embedded emotional controller.	Neural Computing and Applications	2010	DBLP DOI BibTeX RDF
1	Sara Karamati, Zainalabedin Navabi	Using context based methods for test data compression.	ITC	2010	DBLP DOI BibTeX RDF
1	Arezoo Kamran, Mohammad Saeed Jahangiry, Zainalabedin Navabi	Merit based directed random test generation (MDRTG) scheme for combinational circuits.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Amirali Ghofrani, Fatemeh Javaheri, Zainalabedin Navabi	Assertion based verification in TLM.	EWDTS	2010	DBLP DOI BibTeX RDF
1	M. H. Haghbayan, Zainalabedin Navabi	Architecture design and technical methodology for bus testing.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Niki Shakeri, Nastaran Nemati, Majid Nili Ahmadabadi, Zainalabedin Navabi	Near optimal machine learning based random test generation.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Nastaran Nemati, Majid Namaki-Shoushtari, Zainalabedin Navabi	A mixed HDL/PLI test package.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Amirali Ghofrani, Sheis Abolma'ali, Zahra Najafi Haghi, Zainalabedin Navabi	A TLM2.0 assertion library with centralized monitoring approach.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Arezoo Kamran, Nastaran Nemati, Somayeh Sadeghi Kohan, Zainalabedin Navabi	Virtual tester development using HDL/PLI.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Mohammad Hashem Haghbayan, Alireza Yazdanpanah, Sara Karamati, Ramyar Saeedi, Zainalabedin Navabi	Generating test patterns for sequential circuits using random patterns by PLI functions.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Homa Alemzadeh, Marco Cimei, Paolo Prinetto, Zainalabedin Navabi	Facilitating testability of TLM FIFO: SystemC implementations.	EWDTS	2010	DBLP DOI BibTeX RDF
1	M. H. Sargolzaie, Mehdi Semsarzadeh, Mahmoud Reza Hashemi, Zainalabedin Navabi	Low cost error tolerant motion estimation for H.264/AVC standard.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Homa Alemzadeh, Soheil Aminzadeh, Reihaneh Saberi, Zainalabedin Navabi	Code optimization for enhancing SystemC simulation time.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Fatemeh Javaheri, Zainalabedin Navabi	ESL design methodology for architecture exploration.	EWDTS	2010	DBLP DOI BibTeX RDF
1	M. H. Haghbayan, Sara Karamati, Fatemeh Javaheri, Zainalabedin Navabi	Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	S. Behdad Hosseini, Ali Shahabi, Hasan Sohofi, Zainalabedin Navabi	A reconfigurable online BIST for combinational hardware using digital neural networks.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Ali Shahabi, S. Behdad Hosseini, Hasan Sohofi, Zainalabedin Navabi	A partitioning approach to improve reconfigurable neuron-inspired online BIST.	IOLTS	2010	DBLP DOI BibTeX RDF
1	M. R. Jamali, Arash Arami, Masood Deh-Yadegari, Caro Lucas, Zainalabedin Navabi	Emotion on FPGA: Model driven approach.	Expert Syst. Appl.	2009	DBLP DOI BibTeX RDF
1	Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi	Sign Bit Reduction Encoding For Low Power Applications.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Low power multiplier, Signed multiplier, Sign extension, FIR filter, Power reduction, Energy reduction, Bus encoding
1	Nastaran Nemati, Amirhossein Simjour, Amirali Ghofrani, Zainalabedin Navabi	Optimizing Parametric BIST Using Bio-inspired Computing Algorithms.	DFT	2009	DBLP DOI BibTeX RDF
1	Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi	A Selective Trigger Scan Architecture for VLSI Testing.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Delay Testing, Test Compression, Test Application Time, Scan Test, Test Data Volume, Test Power
1	Naghmeh Karimi, Armin Alaghi, Mahshid Sedghi, Zainalabedin Navabi	Online Network-on-Chip Switch Fault Detection and Diagnosis Using Functional Switch Faults.	J. UCS	2008	DBLP BibTeX RDF
1	Homa Alemzadeh, Stefano Di Carlo, Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi	"Plug & Test" at System Level via Testable TLM Primitives.	ITC	2008	DBLP DOI BibTeX RDF
1	Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, Zainalabedin Navabi	NoC Reconfiguration for Utilizing the Largest Fault-free Connected Sub-structure.	ITC	2008	DBLP DOI BibTeX RDF
1	Nadereh Hatami, Zainalabedin Navabi	An advanced method for synthesizing TLM2-based interfaces.	EWDTS	2008	DBLP DOI BibTeX RDF
1	Somayeh Malekshahi, Mahshid Sedghi, Zainalabedin Navabi	Automating Hardware/Software partitioning using dependency Graph.	EWDTS	2008	DBLP DOI BibTeX RDF
1	Najmeh Farajipour, S. Behdad Hosseini, Zainalabedin Navabi	Utilizing HDL simulation engines for accelerating design and test processes.	EWDTS	2008	DBLP DOI BibTeX RDF
1	Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, Mahmood Fathy, Zainalabedin Navabi	Reliable NoC architecture utilizing a robust rerouting algorithm.	EWDTS	2008	DBLP DOI BibTeX RDF
1	Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi	An IEEE 1500 compatible wrapper architecture for testing cores at transaction level.	EWDTS	2008	DBLP DOI BibTeX RDF
1	Negin Mahani, Parnian Mokri, Zainalabedin Navabi	System level hardware design and simulation with SystemAda.	EWDTS	2008	DBLP DOI BibTeX RDF
1	Pejman Lotfi-Kamran, Mehran Massoumi, Mohammad Mirzaei, Zainalabedin Navabi	Enhanced TED: A New Data Structure for RTL Verification.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Mahshid Sedghi, Elnaz Koopahi, Armin Alaghi, Mahmood Fathy, Zainalabedin Navabi	An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Ali Afzali-Kusha, Zainalabedin Navabi	Stall Power Reduction in Pipelined Architecture Processors.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Pejman Lotfi-Kamran, Masoud Daneshtalab, Caro Lucas, Zainalabedin Navabi	BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs.	DATE	2008	DBLP DOI BibTeX RDF
1	Naghmeh Karimi, Soheil Aminzadeh, Saeed Safari, Zainalabedin Navabi	A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing.	IOLTS	2008	DBLP DOI BibTeX RDF
1	Fatemeh Refan, Homa Alemzadeh, Saeed Safari, Paolo Prinetto, Zainalabedin Navabi	Reliability in Application Specific Mesh-Based NoC Architectures.	IOLTS	2008	DBLP DOI BibTeX RDF
1	Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi	Low test application time resource binding for behavioral synthesis.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	CDFG, high-level synthesis, Testability, test synthesis
1	Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi	Simultaneous Reduction of Dynamic and Static Power in Scan Structures	CoRR	2007	DBLP BibTeX RDF
1	Mohammad Hosseinabady, Pejman Lotfi-Kamran, Fabrizio Lombardi, Zainalabedin Navabi	Low overhead DFT using CDFG by modifying controller.	IET Computers & Digital Techniques	2007	DBLP DOI BibTeX RDF
1	Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi	On-Chip Verification of NoCs Using Assertion Processors.	DSD	2007	DBLP DOI BibTeX RDF
1	Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi, Fabrizio Lombardi	RT level reliability enhancement by constructing dynamic TMRS.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	fault tolerant, reliability, TMR, RTL design
1	Nima Honarmand, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi	APDL: A Processor Description Language For Design Space Exploration of Embedded Processors.	FDL	2007	DBLP BibTeX RDF
1	Parisa Razaghi, Shahrzad Mirkhani, Zainalabedin Navabi	A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library.	FDL	2007	DBLP BibTeX RDF
1	Nima Honarmand, Ali Shahabi, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi	High Level Synthesis of Degradable ASICs Using Virtual Binding.	VTS	2007	DBLP DOI BibTeX RDF
1	Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi	A UML Based System Level Failure Rate Assessment Technique for SoC Designs.	VTS	2007	DBLP DOI BibTeX RDF
1	Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi	Using the inter- and intra-switch regularity in NoC switch testing.	DATE	2007	DBLP DOI BibTeX RDF
1	Ali Shahabi, Nima Honarmand, Zainalabedin Navabi	Programmable Routing Tables for Degradable Torus-Based Networks on Chips.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Mohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi	A New Approach for Design and Verification of Transaction Level Models.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, Zainalabedin Navabi	Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode.	DFT	2007	DBLP DOI BibTeX RDF
1	Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi	A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services.	DDECS	2007	DBLP BibTeX RDF
1	Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi	An Analytical Model for Reliability Evaluation of NoC Architectures.	IOLTS	2007	DBLP DOI BibTeX RDF
1	Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale	Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.	IOLTS	2007	DBLP DOI BibTeX RDF
1	Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi	Scan-Based Structure with Reduced Static and Dynamic Power Consumption.	J. Low Power Electronics	2006	DBLP DOI BibTeX RDF
1	Ehsan Atoofian, Zainalabedin Navabi	A Test Approach for Look-Up Table Based FPGAs.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	LUT testing, TPG with LE, BIST, memory testing, FPGA testing
1	Mahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi	An Optimized BIST Architecture for FPGA Look-Up Table Testing.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Masood Deh-Yadegari, Mohsen Nickray, Ali Afzali-Kusha, Zainalabedin Navabi	A New Protocol Stack Model for Network on Chip.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Masoud Daneshtalab, Ali Afzali-Kusha, Ashkan Sobhani, Zainalabedin Navabi, Mohammad D. Mottaghi, Omid Fatemi	Ant colony based routing architecture for minimizing hot spots in NOCs.	SBCCI	2006	DBLP DOI BibTeX RDF	dynamic routing algorithm, network on chip
1	Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi	ByZFAD: a low switching activity architecture for shift-and-add multipliers.	SBCCI	2006	DBLP DOI BibTeX RDF	adder bypass, byZFAD, hot-block ring counter, shiftand-add multiplier, low-power, switching activity
1	Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kusha, Omid Fatemi, Zainalabedin Navabi	NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm.	ASAP	2006	DBLP DOI BibTeX RDF
1	Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi	A concurrent testing method for NoC switches.	DATE	2006	DBLP DOI BibTeX RDF
1	Hadi Esmaeilzadeh, A. Moghimi, E. Ebrahimi, Caro Lucas, Zainalabedin Navabi, A. M. Fakhraie	DCim++: a C++ library for object oriented hardware design and distributed simulation.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi	Low-power and low-latency cluster topology for local traffic NoCs.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi	Instruction-level test methodology for CPU core self-testing.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	CPU core testing, Instruction level testing, test instruction set, BIST, pipelined processor, software-based self testing
1	Zainalabedin Navabi	Digital design and implementation with field programmable devices.		2005	RDF
1	Shahrzad Mirkhani, Zainalabedin Navabi	Enhancing Fault Simulation Performance by Dynamic Fault Clustering.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi	ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi	Sign bit reduction encoding for low power applications.	DAC	2005	DBLP DOI BibTeX RDF	signed multiplier, sing extension, low power, switching activity, bus encoding
1	Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi	TED+: a data structure for microprocessor verification.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Mostafa Naderi, Zainalabedin Navabi	Combination of Assertion and HSAT Methods For Automated Test Vectors Generation.	FDL	2005	DBLP BibTeX RDF
1	Hamid Reza Ghasemi, Zainalabedin Navabi	An Effective VHDL-AMS Simulation Algorithm with Event Partitioning.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi	Simultaneous Reduction of Dynamic and Static Power in Scan Structures.	DATE	2005	DBLP DOI BibTeX RDF
1	Arash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh, Pejman Lotfi-Kamran, Mostafa Naderi, Zainalabedin Navabi	Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Mohammad Alisafaee, Safar Hatami, Ehsan Atoofian, Zainalabedin Navabi, Ali Afzali-Kusha	A low-power scan-path architecture.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi	Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment.	DFT	2005	DBLP DOI BibTeX RDF
1	Farzin Karimi, Zainalabedin Navabi, Waleed Meleis, Fabrizio Lombardi	Using data compression in automatic test equipment for system-on-chip testing.	IEEE T. Instrumentation and Measurement	2004	DBLP DOI BibTeX RDF
1	Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin	A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	BIST architecture, DSP/microprocessor, UTS-DSP, bit/word-oriented memory, memory testing, march test
1	Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi	Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	hierarchical fault simulation, mixed level, delta times, VHDL, register transfer level
1	Bijan Alizadeh, Zainalabedin Navabi	Property Checking based on Hierarchical Integer Equations.	ACSD	2004	DBLP DOI BibTeX RDF
1	Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi	Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Bijan Alizadeh, Zainalabedin Navabi	Using Integer Equations to Check PSL Properties in RT Level Design.	IWSOC	2004	DBLP DOI BibTeX RDF
1	Ehsan Atoofian, Zainalabedin Navabi	A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
1	Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi	The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
1	Elham Safi, Reihaneh Saberi, Zohreh Karimi, Zainalabedin Navabi	Processor Testing Using an ADL Description and Genetic Algorithms.	VLSI-SOC	2003	DBLP BibTeX RDF
1	Ehsan Atoofian, Zainalabedin Navabi	A Low Power BIST Architecture for FPGA Look-Up Table Testing.	VLSI-SOC	2003	DBLP BibTeX RDF
1	Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi	Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing.	VLSI-SOC	2003	DBLP BibTeX RDF
1	Morteza Fayyazi, David R. Kaeli, Zainalabedin Navabi	Dynamic Input Buffer Allocation (DIBA) for Fault Tolerant Ethernet Packet Switching.	PDPTA	2003	DBLP BibTeX RDF
1	Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi	Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment.	Embedded Systems and Applications	2003	DBLP BibTeX RDF
1	Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi	Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.	DFT	2003	DBLP DOI BibTeX RDF
1	Elham Safi, Zohreh Karimi, Maghsoud Abbaspour, Zainalabedin Navabi	Utilizing Various ADL Facets for Instruction Level CPU Test.	MTV	2003	DBLP DOI BibTeX RDF
1	Shahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi	Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
1	Farzin Karimi, Waleed Meleis, Zainalabedin Navabi, Fabrizio Lombardi	Data Compression for System-on-Chip Testing Using ATE. (PDF / PS)	DFT	2002	DBLP DOI BibTeX RDF
1	Hamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi	Fault Simulation for VHDL Based Test Bench and BIST Evaluation.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
1	Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi	Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation.	DATE	2001	DBLP DOI BibTeX RDF
1	Mohammad H. Tehranipour, Zainalabedin Navabi, Seid Mehdi Fakhraie	An efficient BIST method for testing of embedded SRAMs.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Zainalabedin Navabi, Amirhooshang Hashemi, Massoud Eghtesad, Mankuan Michael Vai	Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models.	CHDL	1993	DBLP BibTeX RDF

Publications of "Zainalabedin Navabi" ( http://dblp.L3S.de/Authors/Zainalabedin_Navabi )