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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 4 occurrences of 4 keywords
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Results
Found 18 publication records. Showing 18 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Zdenek Vasícek, Karel Slaný |
Efficient Phenotype Evaluation in Cartesian Genetic Programming.  |
EuroGP  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Lukás Sekanina, Zdenek Vasícek |
A SAT-based fitness function for evolutionary optimization of polymorphic circuits. |
DATE |
2012 |
DBLP BibTeX RDF |
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| 1 | Zdenek Vasícek, Lukás Sekanina |
Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. |
Genetic Programming and Evolvable Machines |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Zdenek Vasícek, Michal Bidlo |
Evolutionary design of robust noise-specific image filters. |
IEEE Congress on Evolutionary Computation |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Zdenek Vasícek, Lukás Sekanina |
A global postsynthesis optimization method for combinational circuits. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Zdenek Vasícek, Lukás Sekanina, Michal Bidlo |
A method for design of impulse bursts noise filters optimized for FPGA implementations. |
DATE |
2010 |
DBLP BibTeX RDF |
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| 1 | Michal Bidlo, Zdenek Vasícek, Karel Slaný |
Sorting Network Development Using Cellular Automata. |
ICES |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Petr Fiser, Jan Schmidt, Zdenek Vasícek, Lukás Sekanina |
On logic synthesis of conventionally hard to synthesize circuits using genetic programming. |
DDECS |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Michal Bidlo, Zdenek Vasícek |
Development of combinational circuits using non-uniform cellular automata: initial results. |
GECCO |
2009 |
DBLP DOI BibTeX RDF |
evolutionary algorithm, combinational circuit, development, cellular automaton |
| 1 | Michal Bidlo, Zdenek Vasícek |
Investigating gate-level evolutionary development of combinational multipliers using enhanced cellular automata-based model. |
IEEE Congress on Evolutionary Computation |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Zdenek Vasícek, Lukás Sekanina |
Hardware Accelerators for Cartesian Genetic Programming. |
EuroGP |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Zdenek Vasícek, Martin Zádník, Lukás Sekanina, Jirí Tobola |
On Evolutionary Synthesis of Linear Transforms in FPGA. |
ICES |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Michal Bidlo, Zdenek Vasícek |
Cellular Automata-Based Development of Combinational and Polymorphic Circuits: A Comparative Study. |
ICES |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Zdenek Vasícek, Lukás Sekanina |
Novel Hardware Implementation of Adaptive Median Filters. |
DDECS |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Zdenek Vasícek, Lukás Sekanina |
An area-efficient alternative to adaptive median filtering in FPGAs. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Zdenek Vasícek, Lukás Sekanina |
Evaluation of a New Platform For Image Filter Evolution. |
AHS |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Zdenek Vasícek, Lukás Sekanina |
Reducing the Area on a Chip Using a Bank of Evolved Filters. |
ICES |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Lukás Sekanina, Zdenek Vasícek |
On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level. |
EvoWorkshops |
2006 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #18 of 18 (100 per page; Change: )
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