| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Omid Sarbishei, Katarzyna Radecka, Zeljko Zilic |
Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Atanu Chattopadhyay, Zeljko Zilic |
Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks. |
IEEE Trans. VLSI Syst. |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hossein Neishaburi, Zeljko Zilic |
An enhanced debug-aware network interface for Network-on-Chip. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason G. Tong, Marc Bottle, Zeljko Zilic |
Assertion clustering for compacted test sequence generation. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephan Bourduas, Zeljko Zilic |
Modeling and evaluation of ring-based interconnects for Network-on-Chip. |
Journal of Systems Architecture - Embedded Systems Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandeep K. Shukla, Prabhat Mishra, Zeljko Zilic |
A Brief History of Multiprocessors and EDA. |
IEEE Design & Test of Computers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Zeljko Zilic, Prabhat Mishra, Sandeep K. Shukla |
Challenges of Rapidly Emerging Consumer Space Multiprocessors. |
IEEE Design & Test of Computers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Prabhat Mishra, Zeljko Zilic, Sandeep K. Shukla |
Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models. |
IEEE Design & Test of Computers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hossein Neishaburi, Zeljko Zilic |
ERAVC: Enhanced reliability aware NoC router. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hossein Neishaburi, Zeljko Zilic |
On Failure Rate Assessment Using an Executable Model of the System. |
DSD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Bojan Mihajlovic, Zeljko Zilic |
Real-time address trace compression for emulated and real system-on-chip processor core debugging. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Zeljko Zilic, Katarzyna Radecka |
Fault tolerant glucose sensor readout and recalibration. |
Wireless Health |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Pang, Katarzyna Radecka, Zeljko Zilic |
An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hossein Neishaburi, Zeljko Zilic |
A distributed AXI-based platform for post-silicon validation. |
VTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hossein Neishaburi, Zeljko Zilic |
A Fault Tolerant Hierarchical Network on Chip Router Architecture. |
DFT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hossein Neishaburi, Zeljko Zilic |
Debug Aware AXI-based Network Interface. |
DFT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hossein Neishaburi, Zeljko Zilic |
Hierarchical Embedded Logic Analyzer for Accurate Root-Cause Analysis. |
DFT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Pang, Katarzyna Radecka, Zeljko Zilic |
Optimization of Imprecise Circuits Represented by Taylor Series and Real-Valued Polynomials. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic |
Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongquan Fan, Zeljko Zilic |
Qualifying Serial Interface Jitter Rapidly and Cost-effectively. |
J. Electronic Testing |
2010 |
DBLP BibTeX RDF |
|
| 1 | Jason G. Tong, Marc Boule, Zeljko Zilic |
Defining and Providing Coverage for Assertion-Based Dynamic Verification. |
J. Electronic Testing |
2010 |
DBLP BibTeX RDF |
|
| 1 | Mohammad Hossein Neishaburi, Zeljko Zilic |
Enabling efficient post-silicon debug by clustering of hardware-assertions. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Yu Pang, Katarzyna Radecka, Zeljko Zilic |
An efficient method to perform range analysis for DSP circuits. |
ICECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Omar Abdelfattah, Andraws Swidan, Zeljko Zilic |
Direct residue-to-analog conversion scheme based on Chinese Remainder Theorem. |
ICECS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongquan Fan, Zeljko Zilic |
Accelerating jitter tolerance qualification for high speed serial interfaces. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongquan Fan, Zeljko Zilic |
A versatile scheme for the validation, testing and debugging of High Speed Serial Interfaces. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jason G. Tong, Marc Boule, Zeljko Zilic |
Airwolf-TG: A test generator for assertion-based dynamic verification. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic |
MYGEN: automata-based on-line test generator for assertion-based verification. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
generator, psl, test vector generation |
| 1 | Mohammad Hossein Neishaburi, Zeljko Zilic |
Reliability aware NoC router architecture using input channel buffer sharing. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
system on chip, network on chip, virtual channel |
| 1 | Atanu Chattopadhyay, Zeljko Zilic |
Serial reconfigurable mismatch-tolerant clock distribution. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
process variation, clock skew, clock networks |
| 1 | Zeljko Zilic |
Designing and Using FPGAs beyond Classical Binary Logic: Opportunities in Nano-Scale Integration Age. |
ISMVL |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ivan Bilicki, Vijay Sundaresan, Daryl Maier, Nikola Grcevski, Zeljko Zilic |
Cache line reservation: exploring a scheme for cache-friendly object allocation. |
CASCON |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Marc Boule, Zeljko Zilic |
Automata-based assertion-checker synthesis of PSL properties. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
assertion checkers, emulation, hardware, automata, PSL, Assertion-Based Verification |
| 1 | Yongquan Fan, Zeljko Zilic |
BER Testing of Communication Interfaces. |
IEEE T. Instrumentation and Measurement |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephan Bourduas, Jean-Samuel Chenard, Zeljko Zilic |
A Quality-Driven Design Approach for NoCs. |
IEEE Design & Test of Computers |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jean-Samuel Chenard, Zeljko Zilic, Milos Prokic |
A Laboratory Setup and Teaching Methodology for Wireless and Mobile Embedded Systems. |
IEEE Trans. Education |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Atanu Chattopadhyay, Zeljko Zilic |
Built-in Clock Skew System for On-line Debug and Repair. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Zeljko Zilic, Katarzyna Radecka |
Scaling and Better Approximating Quantum Fourier Transform by Higher Radices. |
IEEE Trans. Computers |
2007 |
DBLP DOI BibTeX RDF |
quantum computing, Fourier transform, multivalued logic circuits, Walsh functions, multivariable systems |
| 1 | Marc Boule, Jean-Samuel Chenard, Zeljko Zilic |
Debug enhancements in assertion-checker generation. |
IET Computers & Digital Techniques |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Marc Boule, Jean-Samuel Chenard, Zeljko Zilic |
Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongquan Fan, Yi Cai, Zeljko Zilic |
A high accuracy high throughput jitter test solution on ATE for 3GBPS and 6gbps serial-ata. |
ITC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephan Bourduas, Zeljko Zilic |
A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing. |
NOCS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Henry H. Y. Chan, Zeljko Zilic |
Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephan Bourduas, Zeljko Zilic |
Latency Reduction of Global Traffic in Wormhole-Routed Meshes Using Hierarchical Rings for Global Routing. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Marc Boule, Zeljko Zilic |
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Zeljko Zilic, Katarzyna Radecka, Ali Kazamiphur |
Reversible circuit technology mapping from non-reversible specifications. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Atanu Chattopadhyay, Zeljko Zilic |
Reconfigurable Clock Distribution Circuitry. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Henry H. Y. Chan, Zeljko Zilic |
A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Knockaert Radecka, Zeljko Zilic |
Arithmetic transforms for compositions of sequential and imprecise datapaths. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongquan Fan, Yi Cai, Liming Fang, Anant Verma, William Burchanowski, Zeljko Zilic, Sandeep Kumar |
An Accelerated Jitter Tolerance Test Technique on Ate for 1.5GB/S and 3GB/S Serial-ATA. |
ITC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rong Zhang, Zeljko Zilic, Katarzyna Radecka |
Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Marc Boule, Jean-Samuel Chenard, Zeljko Zilic |
Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug. |
ICCD |
2006 |
DBLP BibTeX RDF |
|
| 1 | Atanu Chattopadhyay, Zeljko Zilic |
GALDS: a complete framework for designing multiclock ASICs and SoCs. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jean-Samuel Chenard, Ahmed Usman Khalid, Milos Prokic, Rong Zhang, K.-L. Lim, Atanu Chattopadhyay, Zeljko Zilic |
Expandable and Robust Laboratory for Microprocessor Systems. |
MSE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Henry H. Y. Chan, Zeljko Zilic |
Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
Analog circuit optimization, adjoint analysis, sensitivity analysis, parasitic extraction |
| 1 | Jean-Samuel Chenard, Chun Yiu Chu, Zeljko Zilic, Milica Popovic |
Design methodology for wireless nodes with printed antennas. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
RF CAD, antenna design methodology, printed antenna, printed circuit board |
| 1 | Marc Boule, Zeljko Zilic |
Incorporating Ef.cient Assertion Checkers into Hardware Emulation. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Katarzyna Radecka, Zeljko Zilic |
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
arithmetic transform, Verification, spectral methods, error modeling, Universal Test Set, Reed-Muller transform, Walsh-Hadamard transform |
| 1 | Stuart McCracken, Zeljko Zilic |
Design for Testability of FPGA Blocks. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongquan Fan, Zeljko Zilic, Man Wah Chiang |
A Versatile High Speed Bit Error Rate Testing Scheme. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Henry H. Y. Chan, Zeljko Zilic |
Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Man Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka |
Architectures of Increased Availability Wireless Sensor Network Nodes. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongquan Fan, Zeljko Zilic |
A novel scheme of implementing high speed AWGN communication channel emulators in FPGAs. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka |
FPGA Emulation of Quantum Circuits. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Atanu Chattopadhyay, Zeljko Zilic |
A globally asynchronous locally dynamic system for ASICs and SoCs. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
all-digital clock generation, dynamic clock manager, globally asynchronous locally synchronous system, asynchronous design |
| 1 | Man Wah Chiang, Zeljko Zilic |
Layered Approach to Designing System Test Interfaces. |
VTS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongquan Fan, Zeljko Zilic |
Testing for bit error rate in FPGA communication interfaces. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Marc Boule, Zeljko Zilic |
An FPGA Move Generator for the Game of Chess. |
ICGA Journal |
2002 |
DBLP BibTeX RDF |
|
| 1 | Zeljko Zilic, Zvonko G. Vranesic |
A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields. |
IEEE Trans. Computers |
2002 |
DBLP DOI BibTeX RDF |
Vandermonde matrices, finite fields, Multivariate interpolation, Reed-Muller transform |
| 1 | Zeljko Zilic, Katarzyna Radecka |
The Role of Super-Fast Transforms in Speeding Up Quantum Computations. (PDF / PS) |
ISMVL |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Boris Polianskikh, Zeljko Zilic |
Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection. (PDF / PS) |
ISMVL |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Stuart McCracken, Zeljko Zilic |
FPGA test time reduction through a novel interconnect testing scheme. |
FPGA |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Katarzyna Radecka, Zeljko Zilic |
Identifying Redundant Wire Replacements for Synthesis and Verification. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Katarzyna Radecka, Zeljko Zilic |
Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Zeljko Zilic, Katarzyna Radecka |
: Identifying redundant gate replacements in verification by error modeling. |
ITC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Ian Brynjolfson, Zeljko Zilic |
A new PLL design for clock management applications. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Katarzyna Radecka, Zeljko Zilic |
Arithmetic Transforms for Verifying Compositions of Sequential Datapaths. |
ICCD |
2001 |
DBLP BibTeX RDF |
|
| 1 | R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic |
The NUMAchine Multiprocessor. (PDF / PS) |
ICPP |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Katarzyna Radecka, Zeljko Zilic |
Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. |
VTS |
2000 |
DBLP DOI BibTeX RDF |
arithmetic transforms, functional verification, arithmetic circuits |
| 1 | Ian Brynjolfson, Zeljko Zilic |
FPGA clock management for low power applications (poster abstract). |
FPGA |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Zeljko Zilic |
Alternatives in Teaching System-Building Skills. (PDF / PS) |
MSE |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Zeljko Zilic, Katarzyna Radecka |
On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields. |
ISSAC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Zeljko Zilic, Zvonko G. Vranesic |
Using Decision Diagrams to Design ULMs for FPGAs. |
IEEE Trans. Computers |
1998 |
DBLP DOI BibTeX RDF |
ULMs, classification of logic functions, synthesis of logic functions, FPGAs, BDDs |
| 1 | A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic |
Design and Implementation of the NUMAchine Multiprocessor. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
model checking, verification, guided search |
| 1 | Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic |
Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. |
DAC |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Zeljko Zilic, Zvonko G. Vranesic |
New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms. (PDF / PS) |
ISMVL |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Zeljko Zilic, Zvonko G. Vranesic |
Using BDDs to Design ULMs for FPGAs. |
FPGA |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Zeljko Zilic, Zvonko G. Vranesic |
A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions. |
IEEE Trans. Computers |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Zeljko Zilic, Zvonko G. Vranesic |
Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation. (PDF / PS) |
ISMVL |
1995 |
DBLP DOI BibTeX RDF |
Reed-Muller forms, sparse polynomial interpolation, MVL RM transforms, interpolation, multivalued logic, Reed-Muller codes, polynomial interpolation, incompletely specified functions, computationally efficient algorithm |
| 1 | Zeljko Zilic, Zvonko G. Vranesic |
Current-Mode CMOS Galois Field Circuits. |
ISMVL |
1993 |
DBLP BibTeX RDF |
|
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