Search results for "Zhanping Chen"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Sarvesh H. Kulkarni, Zhanping Chen, Jun He, Lei Jiang, M. Brian Pedersen, Kevin Zhang	A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μ m 2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	Liqiong Wei, Rongtian Zhang, Kaushik Roy, Zhanping Chen, David B. Janes	Vertically integrated SOI circuits for low-power and high-performance applications.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy	IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
1	Zhanping Chen, Liqiong Wei, Kaushik Roy	On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	James Tschanz, Siva Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De	Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.	ISLPED	2001	DBLP DOI BibTeX RDF	dual edge, low power, flip-flops, clocking, triggered, latches
1	Zhanping Chen, Kaushik Roy, Edwin K. P. Chong	Estimation of power dissipation using a novel power macromodelingtechnique.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Zhanping Chen, Liqiong Wei, Kaushik Roy	On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques.	ISQED	2000	DBLP DOI BibTeX RDF
1	Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De	Design and optimization of dual-threshold circuits for low-voltage low-power applications.	IEEE Trans. VLSI Syst.	1999	DBLP DOI BibTeX RDF
1	Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De	Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications.	DAC	1999	DBLP DOI BibTeX RDF
1	Kaushik Roy, Liqiong Wei, Zhanping Chen	Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Zhanping Chen, Kaushik Roy, Tan-Li Chou	Efficient statistical approach to estimate power considering uncertain properties of primary inputs.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF
1	Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy	Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks.	ISLPED	1998	DBLP DOI BibTeX RDF
1	Zhanping Chen, Kaushik Roy	A Power Macromodeling Technique Based on Power Sensitivity.	DAC	1998	DBLP DOI BibTeX RDF	reconfigurable computing, event-driven simulation
1	Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De	Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
1	Zhanping Chen, Kaushik Roy, Edwin K. P. Chong	Estimation of power sensitivity in sequential circuits with power macromodeling application.	ICCAD	1998	DBLP DOI BibTeX RDF
1	Zhanping Chen, Kaushik Roy, Tan-Li Chou	Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs.	ICCAD	1997	DBLP DOI BibTeX RDF	Monte Carlo based approach, maximum bounds, minimum bounds, power dissipation estimation, power sensitivity, primary inputs, signal properties, signal switching, uncertain specifications, logic CAD, CMOS logic circuits, power estimation, CMOS circuits, signal probability, statistical technique

Publications of "Zhanping Chen" ( http://dblp.L3S.de/Authors/Zhanping_Chen )