Search results for "Zili Shao"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Hongxing Wei, Bin Wang, Yi Wang, Zili Shao, Keith C. C. Chan	Staying-alive path planning with energy optimization for mobile robots.	Expert Syst. Appl.	2012	DBLP DOI BibTeX RDF
1	Baokang Zhao, Dan Wang, Zili Shao, Jiannong Cao, Jinshu Su	Privacy aware publishing of successive location information in sensor networks.	Future Generation Comp. Syst.	2012	DBLP DOI BibTeX RDF
1	Duo Liu, Yi Wang, Zili Shao, Minyi Guo, Jingling Xue	Optimally Maximizing Iteration-Level Loop Parallelism.	IEEE Trans. Parallel Distrib. Syst.	2012	DBLP DOI BibTeX RDF
1	Duo Liu, Yi Wang, Zhiwei Qin, Zili Shao, Yong Guan	A Space Reuse Strategy for Flash Translation Layers in SLC NAND Flash Memory Storage Systems.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Tianzheng Wang, Duo Liu, Zili Shao, Chengmo Yang	Write-activity-aware page table management for PCM-based embedded systems.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Duo Liu, Tianzheng Wang, Yi Wang, Zhiwei Qin, Zili Shao	A block-level flash memory management scheme for reducing write activities in PCM-based embedded systems.	DATE	2012	DBLP BibTeX RDF
1	Yi Wang, Luis Angel D. Bathen, Zili Shao, Nikil D. Dutt	3D-FlashMap: A physical-location-aware block mapping strategy for 3D NAND flash memory.	DATE	2012	DBLP BibTeX RDF
1	Zhiwei Qin, Yi Wang, Duo Liu, Zili Shao	Real-Time Flash Translation Layer for NAND Flash Memory Storage Systems.	IEEE Real-Time and Embedded Technology and Applications Symposium	2012	DBLP DOI BibTeX RDF
1	Yanqin Yang, Haijin Yan, Zili Shao, Minyi Guo	Compiler-assisted dynamic scratch-pad memory management with space overlapping for embedded systems.	Softw., Pract. Exper.	2011	DBLP DOI BibTeX RDF
1	Yi Wang, Hui Liu, Duo Liu, Zhiwei Qin, Zili Shao, Edwin Hsing-Mean Sha	Overhead-aware energy optimization for real-time streaming applications on multiprocessor System-on-Chip.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Miao Liu, Duo Liu, Yi Wang, Meng Wang, Zili Shao	On Improving Real-Time Interrupt Latencies of Hybrid Operating Systems with Two-Level Hardware Interrupts.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Zili Shao, Fahim Kawsar	Special issue: Design and optimization for embedded and real-time computing systems and applications.	Journal of Systems Architecture - Embedded Systems Design	2011	DBLP DOI BibTeX RDF
1	Minyi Guo, Zili Shao, Edwin Hsing-Mean Sha	Preface.	J. Comput. Sci. Technol.	2011	DBLP DOI BibTeX RDF
1	Zhiwei Qin, Yi Wang, Duo Liu, Zili Shao, Yong Guan	MNFTL: an efficient flash translation layer for MLC NAND flash memory storage systems.	DAC	2011	DBLP DOI BibTeX RDF
1	Duo Liu, Tianzheng Wang, Yi Wang, Zhiwei Qin, Zili Shao	PCM-FTL: A Write-Activity-Aware NAND Flash Memory Management Scheme for PCM-Based Embedded Systems.	RTSS	2011	DBLP DOI BibTeX RDF
1	Yi Wang, Duo Liu, Zhiwei Qin, Zili Shao	An endurance-enhanced Flash Translation Layer via reuse for NAND flash memory storage systems.	DATE	2011	DBLP DOI BibTeX RDF
1	Zhiwei Qin, Yi Wang, Duo Liu, Zili Shao	A Two-Level Caching Mechanism for Demand-Based Page-Level Address Mapping in NAND Flash Memory Storage Systems.	IEEE Real-Time and Embedded Technology and Applications Symposium	2011	DBLP DOI BibTeX RDF
1	Yanqin Yang, Wenchao Xu, Minyi Guo, Zili Shao	An Efficient Approach of Power Reducing for Scratch-Pad Memory Based Embedded Systems.	ICPP Workshops	2011	DBLP DOI BibTeX RDF	Embedded System, Power, DVFS, Scratch-pad Memory
1	Chun Jason Xue, Jingtong Hu, Zili Shao, Edwin Hsing-Mean Sha	Iterational retiming with partitioning: Loop scheduling with complete memory latency hiding.	ACM Trans. Embedded Comput. Syst.	2010	DBLP DOI BibTeX RDF
1	Yanqin Yang, Meng Wang, Haijin Yan, Zili Shao, Minyi Guo	Dynamic scratch-pad memory management with data pipelining for embedded systems.	Concurrency and Computation: Practice and Experience	2010	DBLP DOI BibTeX RDF
1	Baokang Zhao, Dan Wang, Zili Shao, Jiannong Cao, Keith C. C. Chan, Jinshu Su	An Optimal Algorithm towards Successive Location Privacy in Sensor Networks with Dynamic Programming.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Meng Wang, Yi Wang, Duo Liu, Zhiwei Qin, Zili Shao	Compiler-assisted leakage-aware loop scheduling for embedded VLIW DSP processors.	Journal of Systems and Software	2010	DBLP DOI BibTeX RDF
1	Meikang Qiu, Laurence Tianruo Yang, Zili Shao, Edwin Hsing-Mean Sha	Dynamic and Leakage Energy Minimization With Soft Real-Time Loop Scheduling and Voltage Assignment.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Kai Sun, Meng Wang, Zili Shao, Hui Liu, Hongxing Wei, Tianmiao Wang	Design and Synthesis of a Multiprocessor System-on-Chip Architecture for Real-Time Biomedical Signal Processing in Gamma Cameras.	Signal Processing Systems	2010	DBLP DOI BibTeX RDF
1	Xiyang Liu, Ailong Song, Zili Shao, Chunxiang Li, Ke Chen, Wei Wang	Cluster based architecture synthesis minimizing the resources under time constraint.	ICASSP	2010	DBLP DOI BibTeX RDF
1	Yi Wang, Duo Liu, Zhiwei Qin, Zili Shao	Memory-Aware Optimal Scheduling with Communication Overhead Minimization for Streaming Applications on Chip Multiprocessors.	RTSS	2010	DBLP DOI BibTeX RDF
1	Yi Wang, Duo Liu, Meng Wang, Zhiwei Qin, Zili Shao	Optimal Task Scheduling by Removing Inter-Core Communication Overhead for Streaming Applications on MPSoC.	IEEE Real-Time and Embedded Technology and Applications Symposium	2010	DBLP DOI BibTeX RDF
1	Yi Wang, Duo Liu, Meng Wang, Zhiwei Qin, Zili Shao, Yong Guan	RNFTL: a reuse-aware NAND flash translation layer for flash memory.	LCTES	2010	DBLP DOI BibTeX RDF	reuse, flash memory, wear-leveling, endurance, space utilization
1	Zhiwei Qin, Yi Wang, Duo Liu, Zili Shao	Demand-based block-level address mapping in large-scale NAND flash storage systems.	CODES+ISSS	2010	DBLP DOI BibTeX RDF
1	Minyi Guo, Linfeng Pan, Yanqin Yang, Meng Wang, Zili Shao	An effective state-based predictive approach for leakage energy management on embedded systems.	Design Autom. for Emb. Sys.	2009	DBLP DOI BibTeX RDF
1	Meikang Qiu, Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha	Energy minimization for heterogeneous wireless sensor networks.	J. Embedded Computing	2009	DBLP DOI BibTeX RDF
1	Youtao Zhang, Zili Shao	Special issue of selected papers from EUC 2005.	J. Embedded Computing	2009	DBLP DOI BibTeX RDF
1	Chun Jason Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha	Optimizing parallelism for nested loops with iterational and instructional retiming.	J. Embedded Computing	2009	DBLP DOI BibTeX RDF
1	Hui Liu, Zili Shao, Meng Wang, Junzhao Du, Chun Jason Xue, Zhiping Jia	Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Periodic dependent tasks, Scheduling, Multimedia, Real-time, Dynamic voltage scaling (DVS), Multi-core, Software pipelining, Retiming
1	Meng Wang, Yi Wang, Duo Liu, Zili Shao	Improving the Reliability of Embedded Systems with Cache and SPM.	MASS	2009	DBLP DOI BibTeX RDF
1	Yanqin Yang, Meng Wang, Zili Shao, Minyi Guo	Dynamic Scratch-Pad Memory Management with Data Pipelining for Embedded Systems.	CSE	2009	DBLP DOI BibTeX RDF
1	Meng Wang, Duo Liu, Yi Wang, Zili Shao	Loop scheduling with memory access reduction under register constraints for DSP applications.	SiPS	2009	DBLP DOI BibTeX RDF
1	Chun Jason Xue, Guoliang Xing, Zhaohui Yuan, Zili Shao, Edwin Hsing-Mean Sha	Joint Sleep Scheduling and Mode Assignment in Wireless Cyber-Physical Systems.	ICDCS Workshops	2009	DBLP DOI BibTeX RDF
1	Duo Liu, Zili Shao, Meng Wang, Minyi Guo, Jingling Xue	Optimal loop parallelization for maximizing iteration-level parallelism.	CASES	2009	DBLP DOI BibTeX RDF	iteration-level parallelism, retiming, loop transformation, loop parallelization, data dependence graph
1	Chun Jason Xue, Zhiping Jia, Zili Shao, Meng Wang, Edwin Hsing-Mean Sha	Optimized Address Assignment With Array and Loop Transformations for Minimizing Schedule Length.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong Hu, Zhiping Jia, Weijia Jia, Edwin Hsing-Mean Sha	Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks.	ICASSP	2008	DBLP DOI BibTeX RDF
1	Baokang Zhao, Meng Wang, Zili Shao, Jiannong Cao, Keith C. C. Chan, Jinshu Su	Topology Aware Task Allocation and Scheduling for Real-Time Data Fusion Applications in Networked Embedded Sensor Systems.	RTCSA	2008	DBLP DOI BibTeX RDF
1	Chun Jason Xue, Zhaohui Yuan, Guoliang Xing, Zili Shao, Edwin Hsing-Mean Sha	Energy Efficient Operating Mode Assignment for Real-Time Tasks in Wireless Embedded Systems.	RTCSA	2008	DBLP DOI BibTeX RDF
1	Hui Liu, Zili Shao, Meng Wang, Ping Chen	Overhead-Aware System-Level Joint Energy and Performance Optimization for Streaming Applications on Multiprocessor Systems-on-Chip.	ECRTS	2008	DBLP DOI BibTeX RDF
1	Yanqin Yang, Zili Shao, Linfeng Pan, Minyi Guo	ISOS: Space Overlapping Based on Iteration Access Patterns for Dynamic Scratch-pad Memory Management in Embedded Systems.	ICYCS	2008	DBLP DOI BibTeX RDF
1	Baokang Zhao, Meng Wang, Zili Shao, Jiannong Cao, Keith C. C. Chan, Jinshu Su	Topology-Aware Energy Efficient Task Assignment for Collaborative In-Network Processing in Distributed Sensor Systems.	DIPES	2008	DBLP DOI BibTeX RDF
1	Meng Wang, Zili Shao, Hui Liu, Chun Jason Xue	Minimizing Leakage Energy with Modulo Scheduling for VLIW DSP Processors.	DIPES	2008	DBLP DOI BibTeX RDF
1	Kai Sun, Hongxing Wei, Tianmiao Wang, Meng Wang, Zili Shao, Hui Liu	MPSOC Architectural Design and Synthesis for Real-Time Biomedical Signal Processing in Gamma Cameras.	BIODEVICES	2008	DBLP BibTeX RDF
1	Chun Jason Xue, Edwin Hsing-Mean Sha, Zili Shao, Meikang Qiu	Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints.	DATE	2008	DBLP DOI BibTeX RDF
1	Linfeng Pan, Minyi Guo, Yanqin Yang, Meng Wang, Zili Shao	A State-Based Predictive Approach for Leakage Reduction of Functional Units.	EUC	2008	DBLP DOI BibTeX RDF
1	Baokang Zhao, Dan Wang, Zili Shao, Jiannong Cao, Keith C. C. Chan, Jinshu Su, Yanqin Yang	Towards Successive Privacy Protection in Sensor Networks.	EUC	2008	DBLP DOI BibTeX RDF
1	Yunan Cao, Zili Shao, Meng Wang, Chun Jason Xue, Youdong Chen, Hongxing Wei, Tianmiao Wang	A Formal Specification and Verification Framework for Designing and Verifying Reliable and Dependable Software for Computerized Numerical Control (CNC) Systems.	ICDCS	2008	DBLP DOI BibTeX RDF
1	Shuvra S. Bhattacharyya, Xingshe Zhou, Bing Guo, Zili Shao, Xiangke Liao (eds.)	International Conference on Embedded Software and Systems, ICESS '08, Chengdu, Sichuan, China, July 29-31, 2008.	ICESS	2008	DBLP BibTeX RDF
1	Bin Xiao, Jiannong Cao, Zili Shao, Edwin Hsing-Mean Sha	An efficient algorithm for dynamic shortest path tree update in network routing.	Journal of Communications and Networks	2007	DBLP DOI BibTeX RDF
1	Bin Xiao, Jiannong Cao, Zili Shao, Qingfeng Zhuge, Edwin Hsing-Mean Sha	Analysis and algorithms design for the partition of large-scale adaptive mobile wireless networks.	Computer Communications	2007	DBLP DOI BibTeX RDF
1	Chun Xue, Zili Shao, Edwin Hsing-Mean Sha	Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	optimization, parallelism, loop transformation
1	Meikang Qiu, Zhiping Jia, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha	Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiproceesor DSP.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	real-time, probability, DSP, DVS, assignment
1	Meng Wang, Zili Shao, Chun Xue, Edwin Hsing-Mean Sha	Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors.	RTCSA	2007	DBLP DOI BibTeX RDF
1	Miao Liu, Zili Shao, Meng Wang, Hongxing Wei, Tianmiao Wang	Implementing Hybrid Operating Systems with Two-Level Hardware Interrupts.	RTSS	2007	DBLP DOI BibTeX RDF
1	Meikang Qiu, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha	Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems.	DATE	2007	DBLP DOI BibTeX RDF
1	Tei-Wei Kuo, Edwin Hsing-Mean Sha, Minyi Guo, Laurence Tianruo Yang, Zili Shao (eds.)	Embedded and Ubiquitous Computing, International Conference, EUC 2007, Taipei, Taiwan, December 17-20, 2007, Proceedings	EUC	2007	DBLP BibTeX RDF
1	Guochen Hua, Meng Wang, Zili Shao, Hui Liu, Chun Xue	Real-Time Loop Scheduling with Energy Optimization Via DVS and ABB for Multi-core Embedded System.	EUC	2007	DBLP DOI BibTeX RDF
1	YingZhi Zeng, Baokang Zhao, Jinshu Su, Xia Yan, Zili Shao	A Loop-Based Key Management Scheme for Wireless Sensor Networks.	EUC Workshops	2007	DBLP DOI BibTeX RDF
1	Chun Xue, Zili Shao, Meilin Liu, Qingfeng Zhuge, Edwin Hsing-Mean Sha	Parallel Network Intrusion Detection on Reconfigurable Platforms.	EUC	2007	DBLP DOI BibTeX RDF
1	Tianmiao Wang, Kai Sun, Hongxing Wei, Meng Wang, Zili Shao, Hui Liu	Interconnection Synthesis of MPSoC Architecture for Gamma Cameras.	EUC	2007	DBLP DOI BibTeX RDF
1	Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, Meikang Qiu, Edwin Hsing-Mean Sha	Design optimization and space minimization considering timing and code size via retiming and unfolding.	Microprocessors and Microsystems	2006	DBLP DOI BibTeX RDF
1	Zili Shao, Bin Xiao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha	Loop scheduling with timing and switching-activity minimization for VLIW DSP.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	instruction bus optimization, low-power optimization, compilers, software pipelining, VLIW, retiming, instruction scheduling, loops
1	Zili Shao, Chun Xue, Qingfeng Zhuge, Mei Kang Qiu, Bin Xiao, Edwin Hsing-Mean Sha	Security Protection and Checking for Embedded System Integration against Buffer Overflow Attacks via Hardware/Software.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	hardware/software, Security, embedded system, protection, buffer overflow attack
1	Zili Shao, Jiannong Cao, Keith C. C. Chan, Chun Xue, Edwin Hsing-Mean Sha	Hardware/software optimization for array & pointer boundary checking against buffer overflow attacks.	J. Parallel Distrib. Comput.	2006	DBLP DOI BibTeX RDF
1	Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha	Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture.	ICPADS	2006	DBLP DOI BibTeX RDF
1	Mei Kang Qiu, Chun Xue, Qingfeng Zhuge, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha	Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability.	ASAP	2006	DBLP DOI BibTeX RDF
1	Xiaobo Zhou, Oleg Sokolsky, Lu Yan, Eun-Sun Jung, Zili Shao, Yi Mu, Dong Chun Lee, Daeyoung Kim, Young-Sik Jeong, Cheng-Zhong Xu (eds.)	Emerging Directions in Embedded and Ubiquitous Computing, EUC 2006 Workshops: NCUS, SecUbiq, USN, TRUST, ESO, and MSA, Seoul, Korea, August 1-4, 2006, Proceedings	EUC Workshops	2006	DBLP BibTeX RDF
1	Mei Kang Qiu, Chun Xue, Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin Hsing-Mean Sha	Efficent Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network.	EUC	2006	DBLP DOI BibTeX RDF
1	Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha	Loop Striping: Maximize Parallelism for Nested Loops.	EUC	2006	DBLP DOI BibTeX RDF
1	Bin Xiao, Jiadi Yu, Zili Shao, Minglu Li	Distributed Proximity-Aware Peer Clustering in BitTorrent-Like Peer-to-Peer Networks.	EUC	2006	DBLP DOI BibTeX RDF	Proximity-aware, Clustered BitTorrent (CBT), scalability, peer-to-peer networks, super-peer
1	Zili Shao, Qingfeng Zhuge, Chun Xue, Edwin Hsing-Mean Sha	Efficient Assignment and Scheduling for Heterogeneous DSP Systems.	IEEE Trans. Parallel Distrib. Syst.	2005	DBLP DOI BibTeX RDF	Network-level security and protection
1	Meilin Liu, Zili Shao, Chun Xue, Kevin F. Chen, Edwin Hsing-Mean Sha	Multi-level Loop Fusion with Minimal Code Size.	ISCA PDCS	2005	DBLP BibTeX RDF
1	Ying Chen, Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin Hsing-Mean Sha	Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems.	ICPADS	2005	DBLP DOI BibTeX RDF
1	Zili Shao, Qingfeng Zhuge, Chun Xue, Bin Xiao, Edwin Hsing-Mean Sha	High-level synthesis for DSP applications using heterogeneous functional units.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Meikang Qiu, Edwin Hsing-Mean Sha	Maximum Loop Distribution and Fusion for Two-level Loops Considering Code Size.	ISPAN	2005	DBLP DOI BibTeX RDF
1	Meilin Liu, Qingfeng Zhuge, Zili Shao, Chun Xue, Mei Kang Qiu, Edwin Hsing-Mean Sha	Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs.	EUC	2005	DBLP DOI BibTeX RDF	Loop Distribution, Embedded DSP, Scheduling, Code Size, Loop Fusion
1	Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha	Optimizing Nested Loops with Iterational and Instructional Retiming.	EUC	2005	DBLP DOI BibTeX RDF
1	Mei Kang Qiu, Meilin Liu, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Zili Shao	Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems.	IASTED PDCS	2005	DBLP BibTeX RDF
1	Zili Shao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Bin Xiao	Efficient Array & Pointer Bound Checking Against Buffer Overflow Attacks via Hardware/Software.	ITCC	2005	DBLP DOI BibTeX RDF
1	Chun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha	Iterational retiming: maximize iteration-level parallelism for nested loops.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	optimization, partition, retiming, nested loops
1	Zili Shao, Qingfeng Zhuge, Youtao Zhang, Edwin Hsing-Mean Sha	Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors.	IJHPCN	2004	DBLP DOI BibTeX RDF
1	Meilin Liu, Qingfeng Zhuge, Zili Shao, Kevin F. Chen, Edwin Hsing-Mean Sha	Loop Fusion via Retiming for DSP Applications.	ISCA PDCS	2004	DBLP BibTeX RDF
1	Zili Shao, Qingfeng Zhuge, Yi He, Chun Xue, Meilin Liu, Edwin Hsing-Mean Sha	Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha	Timing Optimization of Nested Loops Considering Code Size for DSP Applications.	ICPP	2004	DBLP DOI BibTeX RDF
1	Zili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao, Edwin Hsing-Mean Sha	Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications.	ASAP	2004	DBLP DOI BibTeX RDF
1	Meilin Liu, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha	General loop fusion technique for nested loops considering timing and code size.	CASES	2004	DBLP DOI BibTeX RDF	embedded DSP, scheduling, retiming, code size, loop fusion
1	Bin Xiao, Jiannong Cao, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha	Dynamic Update of Shortest Path Tree in OSPF.	ISPAN	2004	DBLP DOI BibTeX RDF
1	Zili Shao, Qingfeng Zhuge, Meilin Liu, Edwin Hsing-Mean Sha, Bin Xiao	Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures.	EUC	2004	DBLP DOI BibTeX RDF
1	Chun Xue, Zili Shao, Edwin Hsing-Mean Sha, Bin Xiao	Optimizing Address Assignment for Scheduling Embedded DSPs.	EUC	2004	DBLP DOI BibTeX RDF
1	Zili Shao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Bin Xiao	Security Protection and Checking in Embedded System Integration Against Buffer Overflow Attacks.	ITCC	2004	DBLP DOI BibTeX RDF
1	Bin Xiao, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha	Design and Analysis of Improved Shortest Path Tree Update for Network Routing.	ISCA PDCS	2003	DBLP BibTeX RDF
1	Zili Shao, Qingfeng Zhuge, Yi He, Edwin Hsing-Mean Sha	Defending Embedded Systems Against Buffer Overflow via Hardware/Software.	ACSAC	2003	DBLP DOI BibTeX RDF
1	Zili Shao, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Chantrapornchai	Loop scheduling for minimizing schedule length and switching activities.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-Mean Sha	Design space minimization with timing and code size optimization for embedded DSP.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	retiming, unfolding, code size reduction, DSP processors
1	Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha	Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications. (PDF / PS)	ICPP	2002	DBLP DOI BibTeX RDF	Scheduling, Software pipelining, Retiming, DSP processors

Publications of "Zili Shao" ( http://dblp.L3S.de/Authors/Zili_Shao )