Search results for "accelerators"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Michael Kistler, John A. Gunnels, Daniel A. Brokenshire, Brad Benton	Petascale computing with accelerators.	PPOPP	2009	DBLP DOI BibTeX RDF	hybrid programming models, accelerators
3	Lech Józwiak, Alexander Douglas	Hardware Synthesis for Reconfigurable Heterogeneous Pipelined Accelerators.	ITNG	2008	DBLP DOI BibTeX RDF	re-configurable computing, heterogeneous pipelined accelerators, hardware synthesis, EDA-tool
3	Reiner W. Hartenstein, Jürgen Becker	Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators.	VLSI Design	1997	DBLP DOI BibTeX RDF	data-driven Xputer-based accelerators, CoDe-X, profiling-driven host/accelerator partitioning, resource-driven sequential/structural partitioning, accelerator source code, reconfigurable resources, C dialect, data-procedural language features, parallel programming, partitioning, performance optimization, hardware/software co-design, parallelizing programming environment
3	Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man	Synthesis of pipelined DSP accelerators with dynamic scheduling.	ISSS	1995	DBLP DOI BibTeX RDF	DSP algorithms, FFT butterfly accelerator block, application specific DSP accelerators, highly pipelined data paths, pipelined DSP accelerator synthesis, pipelined bit-parallel hardware, silicon, scheduling, parallel architectures, application specific integrated circuits, dynamic scheduling, pipeline processing, circuit CAD, digital signal processing chips, datapath, controller architecture, network synthesis, run-time schedules
3	Eric William Burger, Guido Dedene	Economics of point accelleration.	EURO-DAC	1990	DBLP DOI BibTeX RDF	CAD Development Methodology, Economics of CAD Systems, Routing Accelerators, Total CAD Systems, Logic Synthesis, Simulation Accelerators
2	Volodymyr V. Kindratenko, Robert Wilhelmson, Robert J. Brunner, Todd J. Martinez, Wen-mei W. Hwu	High-Performance Computing with Accelerators.	Computing in Science and Engineering	2010	DBLP DOI BibTeX RDF	OpenMM, GPU, high-performance computing, OpenMP, accelerators
2	John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel	Cohesion: a hybrid memory model for accelerators.	ISCA	2010	DBLP DOI BibTeX RDF	computer architecture, cache coherence, accelerator
2	Lech Józwiak, Yahya Jan	Architecture Design of Reconfigurable Accelerators for Demanding Applications.	ITNG	2010	DBLP DOI BibTeX RDF	reconfigurable accelerators, advanced applications, design-space exploration, architecture design
2	Tero Rintaluoma, Timo Reinikka, Joona Rouvinen, Jani Boutellier, Pekka Jääskeläinen, Olli Silvén	Programmable Accelerators for Reconfigurable Video Decoder.	SAMOS	2009	DBLP DOI BibTeX RDF
2	Frederico Pratas, Leonel Sousa	Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study.	SAMOS	2009	DBLP DOI BibTeX RDF
2	David M. Kunzman, Laxmikant V. Kalé	Towards a framework for abstracting accelerators in parallel applications: experience with cell.	SC	2009	DBLP DOI BibTeX RDF
2	Rishiyur S. Nikhil	Using GPCE principles for hardware systems and accelerators: (bridging the gap to HW design).	GPCE	2009	DBLP DOI BibTeX RDF	bluespec systemverilog, bsv, energy efficient computing, fpga, high level synthesis, high performance computing, haskell, hardware accelerators, hardware/software codesign, term rewriting systems, hybrid computing
2	Filip Blagojevic, Costin Iancu, Katherine A. Yelick, Matthew Curtis-Maury, Dimitrios S. Nikolopoulos, Benjamin Rose	Scheduling dynamic parallelism on accelerators.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	cooperative scheduling, cell be
2	Liu Ling, Neal Oliver, Bhushan Chitlur, Qigang Wang, Alvin Chen, Wenbo Shen, Zhihong Yu, Arthur Sheiman, Ian McCallum, Joseph Grecco, Henry Mitchel, Dong Liu, Prabhat Gupta	High-performance, energy-efficient platforms using in-socket FPGA accelerators.	FPGA	2009	DBLP DOI BibTeX RDF	in-socket accelerator, fpga, agility
2	Andreas Heinig, Jochen Strunk, Wolfgang Rehm, Heiko Schick	ACCFS - Operating System Integration of Computational Accelerators Using a VFS Approach.	ARC	2009	DBLP DOI BibTeX RDF
2	Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Scott A. Mahlke	Bridging the computation gap between programmable processors and hardwired accelerators.	HPCA	2009	DBLP DOI BibTeX RDF
2	Gregorio Quintana-Ortí, Francisco D. Igual, Enrique S. Quintana-Ortí, Robert A. van de Geijn	Solving dense linear systems on platforms with multiple hardware accelerators.	PPOPP	2009	DBLP DOI BibTeX RDF	algorithms-by-blocks, depencency analysis, dynamic scheduling, out-of-order execution, gpus
2	Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil	Synergistic execution of stream programs on multicores with accelerators.	LCTES	2009	DBLP DOI BibTeX RDF	CUDAa, partitioning, software pipelining, stream programming, GPU programming
2	Ya-shuai Lü, Li Shen, Zhiying Wang, Nong Xiao	Dynamically utilizing computation accelerators for extensible processors in a software approach.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	computation accelerator, ASIP, dynamic binary translation
2	Lars Bauer, Muhammad Shafique, Jörg Henkel	MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	extensible embedded processor, reconfigurable computing, kernel, accelerator, replacement, run-time adaptation
2	Sean Rul, Hans Vandierendonck, Koen De Bosschere	Towards automatic program partitioning.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	off-loading, sub-algorithms, partitioning, accelerators
2	Vikas Aggarwal, Rafael Garcia, Greg Stitt, Alan D. George, Herman Lam	SCF: a device- and language-independent task coordination framework for reconfigurable, heterogeneous systems.	SC-HPRCTA	2009	DBLP DOI BibTeX RDF	communication, coordination, reconfigurable computing, productivity, portability, heterogeneous computing, accelerators
2	Yahya Jan, Lech Józwiak	CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey.	SAMOS	2009	DBLP DOI BibTeX RDF	RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC
2	Ben H. H. Juurlink, Iosif Antochi, Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis	GRAAL: A Framework for Low-Power 3D Graphics Accelerators.	IEEE Computer Graphics and Applications	2008	DBLP DOI BibTeX RDF
2	Fei Xia, Yong Dou, Jiaqing Xu	Families of FPGA-Based Accelerators for BLAST Algorithm with Multi-seeds Detection and Parallel Extension.	BIRD	2008	DBLP DOI BibTeX RDF
2	Sébastien Lafond, Johan Lilius	Interrupt Costs in Embedded System with Short Latency Hardware Accelerators.	ECBS	2008	DBLP DOI BibTeX RDF	Interrupt, Hardware accelerator
2	Toshio Endo, Satoshi Matsuoka	Massive supercomputing coping with heterogeneity of modern accelerators.	IPDPS	2008	DBLP DOI BibTeX RDF
2	Zdenek Vasícek, Lukás Sekanina	Hardware Accelerators for Cartesian Genetic Programming.	EuroGP	2008	DBLP DOI BibTeX RDF
2	Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David M. Bull	DVFS in loop accelerators using BLADES.	DAC	2008	DBLP DOI BibTeX RDF	embedded systems, low power, high-level synthesis, voltage scaling, frequency scaling
2	Ya-shuai Lü, Li Shen, Libo Huang, Zhiying Wang, Nong Xiao	Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques.	DAC	2008	DBLP DOI BibTeX RDF	subgraph covering, VLIW, ASIPs, extensible processors
2	Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy, Ranjani Narayan	Synthesis of application accelerators on Runtime Reconfigurable Hardware.	ASAP	2008	DBLP DOI BibTeX RDF
2	John H. Kelm, Steven S. Lumetta	HybridOS: runtime support for reconfigurable accelerators.	FPGA	2008	DBLP DOI BibTeX RDF	CPU/accelerator architecture, operating system, reconfigurable computing
2	Charles F. Webb	IBM z10: The Next-Generation Mainframe Microprocessor.	IEEE Micro	2008	DBLP DOI BibTeX RDF	high-frequency design, decimal floating-point, reliability, pipeline, microprocessor, branch prediction, accelerators, symmetric multiprocessor (SMP), mainframe, Hot Chips 19
2	Andrew Kinane, Noel E. O'Connor	Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse.	VLSI Signal Processing	2007	DBLP DOI BibTeX RDF	shape adaptive DCT/IDCT, low power, MPEG-4, hardware acceleration, video objects
2	Amir Hormati, Nathan Clark, Scott A. Mahlke	Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping.	CGO	2007	DBLP DOI BibTeX RDF
2	Sadaf R. Alam, Jeffrey S. Vetter, Melissa C. Smith	An Application Specific Memory Characterization Technique for Co-processor Accelerators.	ASAP	2007	DBLP DOI BibTeX RDF
2	Walid A. Najjar	Compiling code accelerators for FPGAs.	CASES	2007	DBLP DOI BibTeX RDF	FPGA code acceleration
2	Günter Knittel	A Compact Shader for FPGA-Based Volume Rendering Accelerators.	ARC	2007	DBLP DOI BibTeX RDF
2	Walid A. Najjar	Compiling code accelerators for FPGAs.	CODES+ISSS	2007	DBLP DOI BibTeX RDF
2	Maurizio Paganini	Nomadik®: A Mobile Multimedia Application Processor Platform.	ASP-DAC	2007	DBLP DOI BibTeX RDF	mobile multimedia application processor platform, Nomadik platform, industry standard host processor, low-power DSP, hardware accelerators
2	Somsubhra Mondal, Seda Ogrenci Memik, Nikolaos Bellas	Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators.	FPL	2006	DBLP DOI BibTeX RDF
2	Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan Linzmeier	FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators.	IPDPS	2006	DBLP DOI BibTeX RDF
2	Nathan Clark, Amir Hormati, Scott A. Mahlke, Sami Yehia	Scalable subgraph mapping for acyclic computation accelerators.	CASES	2006	DBLP DOI BibTeX RDF	compilation, embedded processors
2	Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott A. Mahlke	Increasing hardware efficiency with multifunction loop accelerators.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	multifunction design, high-level synthesis, modulo scheduling, loop accelerator, application-specific hardware
2	Jeff H. Derby, Robert K. Montoye, José Moreira	VICTORIA: VMX indirect compute technology oriented towards in-line acceleration.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	VMX, SIMD, accelerators, powerPC
2	Kenneth J. Turner	Test generation for radiotherapy accelerators.	STTT	2005	DBLP DOI BibTeX RDF	Lotos (Language Of Temporal Ordering Specification), Test generation, Accelerator, Radiotherapy
2	Sami Yehia, Nathan Clark, Scott A. Mahlke, Krisztián Flautner	Exploring the design space of LUT-based transparent accelerators.	CASES	2005	DBLP DOI BibTeX RDF	accelerator design, embedded processing, efficient computation
2	Miljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne	Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	virtual machine, synthesis, accelerator
2	Alberto Ferrante, Vincenzo Piuri, Fabien Castanier	A QoS-enabled packet scheduling algorithm for IPSec multi-accelerator based systems.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	cryptographic accelerators, scheduling, QoS, quality of service, IPSec
2	Charlie Johnson, Jeff Welser	Future processors: flexible and modular.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	multiprocessor, SoC, accelerators
2	Pradip Bose	Presilicon modeling: challenges in the late CMOS era.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Integrated microarchitectures, special purpose accelerators, scalable on-chip interconnection network, presilicon modeling, CMOS
2	David Guevorkian, Petri Liuha, Aki Launiainen, Ville Lappalainen	A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier Structures.	SAMOS	2004	DBLP DOI BibTeX RDF
2	Kaspar Arzner, Loukas Vlahos, Bernard Knaepen, Nicolas Denewet	Statistical Properties of Dissipative MHD Accelerators.	PARA	2004	DBLP DOI BibTeX RDF
2	Manjunath Kudlur, Kevin Fan, Michael L. Chu, Scott A. Mahlke	Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators.	ASAP	2004	DBLP DOI BibTeX RDF
2	Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha	GRAAL - A Development Framework for Embedded Graphics Accelerators.	DATE	2004	DBLP DOI BibTeX RDF
2	Valery Sklyarov, Iouliia Skliarova, Pedro Almeida, Manuel Almeida	High-Level Design Tools for FPGA-Based Combinatorial Accelerators.	FPL	2003	DBLP DOI BibTeX RDF
2	Ji Qiang, Miguel A. Furman, Robert D. Ryne	Parallel Particle-In-Cell Simulation of Colliding Beams in High Energy Accelerators.	SC	2003	DBLP DOI BibTeX RDF
2	Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman	PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators.	VLSI Signal Processing	2002	DBLP DOI BibTeX RDF	high-level hardware synthesis, automatic parallelization, datapath synthesis
2	Kenneth J. Turner, Qian Bing	Protocol Techniques for Testing Radiotherapy Accelerators.	FORTE	2002	DBLP DOI BibTeX RDF
2	Akira Miyashita, Toshihito Fujiwara, Tsutomu Maruyama	A Placement/Routing Approach for FPGA Accelerators.	FPL	2002	DBLP DOI BibTeX RDF
2	Ricardo A. Fonseca, Luís O. Silva, F. S. Tsung, Viktor K. Decyk, Wei Lu, Chuang Ren, Warren B. Mori, S. Deng, S. Lee, T. Katsouleas, J. C. Adam	OSIRIS: A Three-Dimensional, Fully Relativistic Particle in Cell Code for Modeling Plasma Based Accelerators.	International Conference on Computational Science	2002	DBLP DOI BibTeX RDF
2	Andreas Adelmann, Derek Feichtinger	Generic Large Scale 3D Visualization of Accelerators and Beam Lines.	International Conference on Computational Science	2002	DBLP DOI BibTeX RDF
2	James J. Feenan Jr., Patrick Fry, Ming Lei	Clustering Web Accelerators. (PDF / PS)	WECWIS	2002	DBLP DOI BibTeX RDF
2	Emil Jovanov, Veljko M. Milutinovic, Ali R. Hurson	Acceleration of Nonnumeric Operations Using Hardware Support for the Ordered Table Hashing Algorithms.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	nonnumeric processing, searching, sorting, hashing, hardware accelerators, Database operations
2	Steven Derrien, Sanjay V. Rajopadhye	Loop Tiling for Reconfigurable Accelerators.	FPL	2001	DBLP DOI BibTeX RDF
2	Shail Aditya, Michael S. Schlansker	ShiftQ: a bufferred interconnect for custom loop accelerators.	CASES	2001	DBLP DOI BibTeX RDF
2	Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider	High-Level Synthesis of Nonprogrammable Hardware Accelerators.	ASAP	2000	DBLP DOI BibTeX RDF
2	Ruth Sivilotti, Young Cho, Wen-King Su, Danny Cohen, Brian Bray	Scalable Network Based FPGA Accelerators for an Automatic Target Recognition Application.	FCCM	1998	DBLP DOI BibTeX RDF
2	Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man	Synthesis of pipelined DSP accelerators with dynamic scheduling.	IEEE Trans. VLSI Syst.	1997	DBLP DOI BibTeX RDF
2	Reiner W. Hartenstein, Jürgen Becker	A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators.	HICSS	1997	DBLP DOI BibTeX RDF
2	Reiner W. Hartenstein, Jürgen Becker	Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators.	CODES	1997	DBLP DOI BibTeX RDF	structural programmable co-processors, design space exploration, performance estimation
2	K. M. Sammut, S. R. Jones	Arithmetic Unit Design for Neural Accelerators: Cost Performance Issues.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	linear array accelerators, arithmetic constructs, instruction set measurements, cost/performance trade-offs, Neural networks
2	Paolo Ienne	Horizontal Microcode Compaction for Programmable Systolic Accelerators.	ASAP	1995	DBLP DOI BibTeX RDF	Horizontal Microcode, Microcode Compaction, Programmable Systolic Arrays, Neural Networks
1	Tobias Schumacher, Christian Plessl, Marco Platzner	IMORC: An infrastructure and architecture template for implementing high-performance reconfigurable FPGA accelerators.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Ramon Doallo, Margarita Amor, Basilio B. Fraguela	Special issue editorial: Exploitation of hardware accelerators.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Uwe Meyer-Bäse, Guillermo Botella Juan, Soumak Mookherjee, Encarnación Castillo, Antonio García	Energy optimization of Application-Specific Instruction-Set Processors by using hardware accelerators in semicustom ICs technology.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Rainer Buchty, Vincent Heuveline, Wolfgang Karl, Jan-Philipp Weiss	A survey on hardware-aware and heterogeneous computing on multicore processors and accelerators.	Concurrency and Computation: Practice and Experience	2012	DBLP DOI BibTeX RDF
1	Daniel Hackenberg, Guido Juckeland, Holger Brunst	Performance analysis of multi-level parallelism: inter-node, intra-node and hardware accelerators.	Concurrency and Computation: Practice and Experience	2012	DBLP DOI BibTeX RDF
1	Samer Al-Kiswany, Abdullah Gharaibeh, Matei Ripeanu	GPUs as Storage System Accelerators	CoRR	2012	DBLP BibTeX RDF
1	Kah-Hyong Chang, Paramesran Raveendran, Barmak Honarvar Shakibaei Asli, Chern-Loon Lim	Efficient Hardware Accelerators for the Computation of Tchebichef Moments.	IEEE Trans. Circuits Syst. Video Techn.	2012	DBLP DOI BibTeX RDF
1	Richard Membarth, Jan-Hugo Lupp, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert	Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging.	ARCS	2012	DBLP DOI BibTeX RDF
1	Brian Miller, Derek Brasili, Tim Kiszely, Rob Kuhn, Rahul Mehrotra, Manan Salvi, Mandar Kulkarni, Anand Varadharajan, Shi-Huang Yin, William Lin, Adam Hughes, Bill Stysiack, Vasu Kandadi, Ilan Pragaspathi, Dan Hartman, David Carlson, Vishnu Yalala, Thucydides Xanthopoulos, Scott Meninger, Ethan Crain, Mark Spaeth, Akin Aina, Suresh Balasubramanian, Joe Vulih, Pragati Tiwary, David Lin, Richard Kessler, Bruce Fishbein, Anil Jain	A 32-core RISC microprocessor with network accelerators, power management and testability features.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Muhammad Shafiq, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé	BSArc: blacksmith streaming architecture for HPC accelerators.	Conf. Computing Frontiers	2012	DBLP DOI BibTeX RDF
1	Sungho Park, Yong Cheol Peter Cho, Kevin M. Irick, Vijaykrishnan Narayanan	A reconfigurable platform for the design and verification of domain-specific accelerators.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Alexandru Amaricai, Oana Boncalo	Automatic Generation of FPGA Hardware Accelerators for Graphics Applications.	PECCS	2012	DBLP BibTeX RDF
1	Samuel Bayliss, George A. Constantinides	Optimizing SDRAM bandwidth for custom FPGA loop accelerators.	FPGA	2012	DBLP DOI BibTeX RDF
1	Bashir M. Al-Hashimi, Ronny Morad	Accelerators and emulators: Can they become the platform of choice for hardware verification?	DATE	2012	DBLP BibTeX RDF
1	Guilherme Cox, Cleomar P. Silva, Leandro F. Cupertino, Cristiana Bentes, Ricardo C. Farias	Exploring parallelism in volume ray casting: understanding the programming issues of multithreaded accelerators.	PMAM	2012	DBLP DOI BibTeX RDF
1	Hritam Dutta	Synthesis and exploration of loop accelerators for systems-on-a-chip.		2011	RDF
1	David M. Kunzman, Laxmikant V. Kalé	Programming heterogeneous clusters with accelerators using object-based programming.	Scientific Programming	2011	DBLP DOI BibTeX RDF
1	Emanuele Ruffaldi, Alessandro Filippeschi, Carlo Alberto Avizzano, Benoît G. Bardy, Daniel Gopher, Massimo Bergamasco	Feedback, Affordances, and Accelerators for Training Sports in Virtual Environments.	Presence	2011	DBLP DOI BibTeX RDF
1	Knut Stolze, Felix Beier, Oliver Koeth, Kai-Uwe Sattler	Integrating Cluster-Based Main-Memory Accelerators in Relational Data Warehouse Systems.	Datenbank-Spektrum	2011	DBLP DOI BibTeX RDF
1	Jean-Luc Vay, Cameron G. R. Geddes, Estelle Cormier-Michel, David P. Grote	Numerical methods for instability mitigation in the modeling of laser wakefield accelerators in a Lorentz-boosted frame.	J. Comput. Physics	2011	DBLP DOI BibTeX RDF
1	T. F. Silva, M. N. Martins	Statistical treatment of misalignments in particle accelerators.	Computer Physics Communications	2011	DBLP DOI BibTeX RDF
1	John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel	Cohesion: An Adaptive Hybrid Memory Model for Accelerators.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	David A. Bader, David R. Kaeli, Volodymyr V. Kindratenko	Guest Editor's Introduction: Special Issue on High-Performance Computing with Accelerators.	IEEE Trans. Parallel Distrib. Syst.	2011	DBLP DOI BibTeX RDF
1	Rick Weber, Akila Gothandaraman, Robert J. Hinde, Gregory D. Peterson	Comparing Hardware Accelerators in Scientific Applications: A Case Study.	IEEE Trans. Parallel Distrib. Syst.	2011	DBLP DOI BibTeX RDF	FPGA, GPU, multicore, computational science, CUDA, Accelerator, OpenCL
1	Greg Stitt, Frank Vahid	Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Navin Michael, A. Prasad Vinod, Christophe Moy, Jacques Palicot	Design of Multistandard Channelization Accelerators for Software Defined Radio Handsets.	IEEE Transactions on Signal Processing	2011	DBLP DOI BibTeX RDF
1	M. Mustafa Rafique, Ali Raza Butt, Dimitrios S. Nikolopoulos	A capabilities-aware framework for using computational accelerators in data-intensive computing.	J. Parallel Distrib. Comput.	2011	DBLP DOI BibTeX RDF