Search results for "adders"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
6	Akhilesh Tyagi	A Reduced-Area Scheme for Carry-Select Adders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	reduced-area, conditional-sum adders, carry-chain evaluations, gate-count, carry-ripple, classical carry-select, logic design, adders, logic circuits, gate-delay, parallel-prefix adders, analytic evaluation, area-efficient, carry-skip adders, carry-select adders
5	Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos	High-Speed Parallel-Prefix Modulo 2n-1 Adders.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Modulo $2^n-1$ adders, VLSI design, parallel-prefix adders, carry look-ahead adders
5	Hans Lindkvist, Per Andersson	Dynamic CMOS circuit techniques for delay and power reduction in parallel adders .	ARVLSI	1995	DBLP DOI BibTeX RDF	dynamic CMOS circuit techniques, delay reduction, parallel adders, high-speed adders, Manchester-carry chains, clock/data precharged dynamic logic blocks, carry calculation trees, parallel processing, VLSI, delays, logic design, digital arithmetic, power consumption, adders, CMOS logic circuits, power reduction, carry logic
4	Javier D. Bruguera, Tomás Lang	Multilevel Reverse-Carry Addition: Single and Dual Adders.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	prefix adders, dual adders, most-significant-carry detection, computer arithmetic, VLSI design
4	Luigi Dadda, Vincenzo Piuri	Pipelined Adders.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	high-speed adders, high-throughput adders, skewed arithmetic, Adders, pipelined computation
4	W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi	A 16-bit x 16-bit 1.2 /spl mu/ CMOS multiplier with low latency vector merging.	VLSI Design	1995	DBLP DOI BibTeX RDF	CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
4	Stanislaw J. Piestrak	Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	residue generators, multioperand modular adders, arithmetic error detecting codes, binary-to-residue number system, residue generator, digital arithmetic, adders, Chinese remainder theorem, residue number system, arithmetic codes, residue arithmetic, carry-save adders
4	Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija	Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	delay optimisation, block carry-lookahead adders, multidimensional dynamic programming, worst-case carry propagation delays, minimum latency, fanin, dynamic programming, digital arithmetic, adders, gate delays, carry logic, fanout, critical path delay, carry-skip adders
4	Hung Chi Lai, Saburo Muroga	Logic Networks of Carry-Save Adders.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	parallel adder in double-rail input logic, Carry?save adders, input bundles, multioperand adders, NAND gates, NOR gates, output bundles, logic design, multipliers, full adders
4	Hung Chi Lai, Saburo Muroga	Minimum Parallel Binary Adders with NOR (NAND) Gates.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	NOR gates, carry-ripple adders, minimum adders, NAND gates, logic design, Adders
3	Chien-Hung Lin, Shu-Chung Yi, Jin-Jia Chen	Low Power Adders Design for Portable Video Terminal.	IIH-MSP	2008	DBLP DOI BibTeX RDF	low power adders, portable video terminal, Full adders
3	Giacomo Paci, Paul Marchal, Luca Benini	Exploration of Low Power Adders for a SIMD Data Path.	ASP-DAC	2007	DBLP DOI BibTeX RDF	SIMD data path, low power adders
3	Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng, John Lillis	Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space.	ASP-DAC	2007	DBLP DOI BibTeX RDF	optimum prefix adders, static power consumptions, dynamic power consumptions, high-level synthesis, integer linear programming, buffer insertion, gate sizing, power models, ASIC designs, parallel prefix adder, binary adder
3	Riyaz A. Patel, Mohammed Benaissa, Said Boussakta	Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Modulo 2n-1 adders, One's complement adders, computer arithmetic, VLSI design, parallel-prefix adders
3	Giorgos Dimitrakopoulos, Dimitris Nikolos	High-Speed Parallel-Prefix VLSI Ling Adders.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	parallel-prefix carry computation, computer arithmetic, VLSI design, Adders
3	Peter Kornerup	Reviewing 4-to-2 Adders for Multi-Operand Addition.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	redundant adders, digit sets, digit encodings, multiplier trees
3	Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian	Easily Testable Cellular Carry Lookahead Adders.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	cellular carry lookahead adders, linear-testability, design-for-testability, cell fault model
3	Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos	Modulo 2n±1 Adder Design Using Select-Prefix Blocks.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	modulo 2n± 1 adders, select-prefix adders, computer arithmetic, VLSI architectures
3	Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos	Diminished-One Modulo 2n+1 Adder Design.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Modulo $big. 2^{rm n}+1bigr.$ addition, carry look-ahead addition, diminished-one number representation, VLSI adders, parallel-prefix adders
3	Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer	Testing Schemes for FIR Filter Structures.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Complex multipliers, sign-extended adders, trees of adders, design for testability, FIR filters, state coverage, pseudoexhaustive testing, cell fault model
3	Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald	Self-Timed Carry-Lookahead Adders.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	delay-insenstive circuits, tree iterative circuits, CMOS, Self-timed circuits, carry-lookahead adders
3	José Fernández Ramos, Alfonso Gago Bohórquez	Two Operand Binary Adders with Threshold Logic.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	neural networks, logic design, computer arithmetic, Threshold logic, threshold gate, binary adders
3	Seiji Kajihara, Tsutomu Sasao	On the Adders with Minimum Tests.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	ripple carry adder, minimum test set, test generation, stuck-at fault, carry look-ahead adders
3	Steven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel	Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders.	ASYNC	1997	DBLP DOI BibTeX RDF	completion detection, Brent-Kung, Carry-Bypass, asynchronous, adders, hazards, high-performance design
3	Priyadarsan Patra, Donald S. Fussell	Fully asynchronous, robust, high-throughput arithmetic structures.	VLSI Design	1995	DBLP DOI BibTeX RDF	fully asynchronous structures, high-throughput arithmetic structures, bit serial adders, scaleability, VLSI, digital arithmetic, asynchronous circuits, adders, integrated logic circuits, multiplying circuits, RSA cryptosystems, delay-insensitive, bit serial multipliers
3	Vitit Kantabutra	Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	accelerated two-level carry-skip adders, bit positions, bimodal, CMOS VLSI, 12.6 sec, VLSI, delays, adders, CMOS integrated circuits, unimodal, 2 micron
3	Vitit Kantabutra	Designing Optimum One-Level Carry-Skip Adders.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	one-level, 64 bit, 6.23 ns, logic design, digital simulation, adders, SPICE simulation, carry-skip adders, 1 micron
3	Branislava Perunicic, Salim Lakhani, Veljko M. Milutinovic	Stochastic Modeling and Analysis of Propagation Delays in GaAs Adders.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	GaAs adders, stochastic changes, III-V semiconductors, probability, combinational circuits, stochastic modelling, stochastic processes, adders, combinatorial circuits, propagation delays, gate delays, GaAs, gallium arsenide, probability distribution function
3	Bernd Becker	Efficient Testing of Optimal Time Adders.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	optimal time adders, conditional sum adder, VLSI, logic testing, adders, integrated logic circuits, VLSI chip, carry look-ahead adder
2	Jeff Rebacz, Erdal Oruklu, Jafar Saniie	High performance signed-digit decimal adders.	EIT	2009	DBLP DOI BibTeX RDF
2	Javier Hormigo, Manuel Ortiz, Francisco J. Quiles, Francisco J. Jaime, Julio Villalba, Emilio L. Zapata	Efficient Implementation of Carry-Save Adders in FPGAs.	ASAP	2009	DBLP DOI BibTeX RDF
2	Fatemeh Eslami, Amirali Baniasadi, Mostafa Farahani	Application Specific Transistor Sizing for Low Power Full Adders.	ASAP	2009	DBLP DOI BibTeX RDF
2	Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas	Efficient Reversible Logic Design of BCD Subtractors.	Transactions on Computational Science	2009	DBLP DOI BibTeX RDF	BCD subtractors, BCD adders, Reversible logic
2	Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi	A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
2	Robert T. Grisamore, Earl E. Swartzlander Jr.	Negative Save Sign Extension for Multi-term Adders and Multipliers.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	adder trees, multi-term adders, two’s complement arithmetic, sign extension, multipliers
2	Haridimos T. Vergos, Dimitris Bakalis	On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components.	DSD	2008	DBLP DOI BibTeX RDF
2	Hirokatsu Shirahama, Takahiro Hanyu	Design of High-Performance Quaternary Adders Based on Output-Generator Sharing.	ISMVL	2008	DBLP DOI BibTeX RDF	Carry pre-addition, Differential-pair circuitry, Voltage-mode circuit, Transfer-gate circuitry, Current-mode circuit
2	Álvaro Vázquez, Elisardo Antelo	New insights on Ling adders.	ASAP	2008	DBLP DOI BibTeX RDF
2	Yi Zhu, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng	Timing-power optimization for mixed-radix Ling adders by integer linear programming.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Wenjing Rao, Alex Orailoglu	Towards fault tolerant parallel prefix adders in nanoelectronic systems.	DATE	2008	DBLP DOI BibTeX RDF
2	Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima	ROM based logic (RBL) design: High-performance and low-power adders.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Erdal Oruklu, Vibhuti B. Dave, Jafar Saniie	Performance analysis of flagged prefix adders with logical effort.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Zine Abid, Wei Wang 0003	New designs of Redundant-Binary full Adders and its applications.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Julien Francq, Jean-Baptiste Rigaud, Pascal Manet, Assia Tria, Arnaud Tisserand	Error Detection for Borrow-Save Adders Dedicated to ECC Unit.	FDTC	2008	DBLP DOI BibTeX RDF
2	Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga	Synthesis of parallel prefix adders considering switching activities.	ICCD	2008	DBLP DOI BibTeX RDF
2	Levent Aksoy, Ece Olcay Günes	Area optimization algorithms in high-speed digital FIR filter synthesis.	SBCCI	2008	DBLP DOI BibTeX RDF	high-speed filter design, multiple constant multiplications, subexpression sharing, area optimization, carry-save adders
2	Michael Kirkedal Thomsen, Holger Bock Axelsen	Parallel Optimization of a Reversible (Quantum) Ripple-Carry Adder.	UC	2008	DBLP DOI BibTeX RDF	quantum computing, adders, circuits, Reversible computing
2	Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy	Fine-Grained Redundancy in Adders.	ISQED	2007	DBLP DOI BibTeX RDF
2	Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas	Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Alexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo	Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition.	DSD	2007	DBLP DOI BibTeX RDF
2	Taeko Matsunaga, Yusuke Matsunaga	Area minimization algorithm for parallel prefix adders under bitwise delay constraints.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	arithmetic synthesis, dynamic programming, parallel prefix adder
2	Ismo Hänninen, Jarmo Takala	Robust Adders Based on Quantum-Dot Cellular Automata.	ASAP	2007	DBLP DOI BibTeX RDF
2	A. Neslin Ismailoglu, Murat Askar	Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Himanshu Thapliyal, A. Prasad Vinod	Designing Efficient Online Testable Reversible Adders With New Reversible Gate.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Massimo Alioto, Gaetano Palumbo	Delay Variability Due to Supply Variations in Transmission-Gate Full Adders.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Jeong-Gun Lee, Jeong-A. Lee, Byeong-Seok Lee, Milos D. Ercegovac	A Design Method for Heterogeneous Adders.	ICESS	2007	DBLP DOI BibTeX RDF
2	Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii	Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study.	ICESS	2007	DBLP DOI BibTeX RDF
2	Sheng Sun, Carl Sechen	Post-layout comparison of high performance 64b static adders in energy-delay space.	ICCD	2007	DBLP DOI BibTeX RDF
2	Luigi Dadda	Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	multioperand adders, Computer arithmetic, hardware design, decimal arithmetic
2	M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas	New and Improved Architectures for Montgomery Modular Multiplication.	MONET	2007	DBLP DOI BibTeX RDF	reconfigurable multiplier, scalable multiplier, RSA, ECC, carry save adders, Montgomery modular multiplication
2	Gian-Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano	Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Fault tolerance, error checking, high-speed arithmetic
2	Ilya Obridko, Ran Ginosar	Minimal Energy Asynchronous Dynamic Adders.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Sumeer Goel, Ashok Kumar, Magdy A. Bayoumi	Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Kavallur Gopi Smitha, H. A. H. Fahmy, A. Prasad Vinod	Redundant Adders Consume Less Energy.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas	Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format.	VLSI Design	2006	DBLP DOI BibTeX RDF
2	Johannes Grad, James E. Stine	Low power binary addition using carry increment adders.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Ann Majchrzak, Christian Wagner, Dave Yates	Corporate wiki users: results of a survey.	Int. Sym. Wikis	2006	DBLP DOI BibTeX RDF	corporate wiki, knowledge contribution, knowledge restructuring, survey, adders, knowledge reuse, synthesizers
2	Robert D. Kenney, Michael J. Schulte	High-Speed Multioperand Decimal Adders.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	multioperand adders, Computer arithmetic, hardware designs, decimal arithmetic
2	Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy	Comparison of high-performance VLSI adders in the energy-delay space.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders.	ISQED	2005	DBLP DOI BibTeX RDF
2	Julio Villalba, Javier Hormigo, Jose M. Prades, Emilio L. Zapata	On-line Multioperand Addition Based on On-line Full Adders.	ASAP	2005	DBLP DOI BibTeX RDF
2	Rumi Zhang, Wei Wang 0003, Konrad Walus, Graham A. Jullien	Performance comparison of quantum-dot cellular automata adders.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Jin-Fu Li, Jiunn-Der Yu, Yu-Jen Huang	A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability.	ISCAS	2005	DBLP DOI BibTeX RDF
2	George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis	Test Generation Methodology for High-Speed Floating Point Adders.	IOLTS	2005	DBLP DOI BibTeX RDF
2	James Alfred Walker, Julian Francis Miller	Investigating the performance of module acquisition in cartesian genetic programming.	GECCO	2005	DBLP DOI BibTeX RDF	digital adders, digital comparators, digital multipliers, modularity, cartesian genetic programming, computational effort, module acquisition
2	Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos	Fast Parallel-Prefix Modulo 2^n+1 Adders.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
2	Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis	Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach.	ISVLSI	2004	DBLP DOI BibTeX RDF
2	Giorgos Dimitrakopoulos, P. Kolovos, P. Kalogerakis, Dimitris Nikolos	Design of High-Speed Low-Power Parallel-Prefix VLSI Adders.	PATMOS	2004	DBLP DOI BibTeX RDF
2	Kenny Johansson, Oscar Gustafsson, Lars Wanhammar	Power Estimation for Ripple-Carry Adders with Correlated Input Data.	PATMOS	2004	DBLP DOI BibTeX RDF
2	Jin-Fu Li, Chih-Chiang Hsu	Efficient Test Methodologies for Conditional Sum Adders.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
2	Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris	Fast adders in modern FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF
2	Matthew M. Ziegler, Mircea R. Stan	A Unified Design Space for Regular Parallel Prefix Adders.	DATE	2004	DBLP DOI BibTeX RDF	Kogge-Stone adder, Han-Carlson adder, Brent-Kung adder, parallel prefix adder
2	Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou	Deterministic BIST for RNS Adders.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	deterministic and pseudorandom tests, formal test sets, Built-In Self-Test, Residue Number System
2	Jia Di, Jiann S. Yuan, Ronald F. DeMara	High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders.	ISVLSI	2003	DBLP DOI BibTeX RDF
2	João Leonardo Fragoso, Gilles Sicard, Marc Renaudin	Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders.	PATMOS	2003	DBLP DOI BibTeX RDF
2	João Leonardo Fragoso, Gilles Sicard, Marc Renaudin	Automatic Generation of 1-of-M QDI Asynchronous Adders.	SBCCI	2003	DBLP DOI BibTeX RDF
2	Jean-Luc Beuchat	Some Modular Adders and Multipliers for Field Programmable Gate Arrays.	IPDPS	2003	DBLP DOI BibTeX RDF	modulo m addition, modulo m multiplication, FPGA, Computer arithmetic
2	Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou	A Family of Parallel-Pre.x Modulo 2n - 1 Adders.	ASAP	2003	DBLP DOI BibTeX RDF
2	Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou	A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy	Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
2	Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.	Quadruple Time Redundancy Adders.	DFT	2003	DBLP DOI BibTeX RDF
2	D. G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou	An Efficient BIST scheme for High-Speed Adders.	IOLTS	2003	DBLP DOI BibTeX RDF
2	Jianhua Liu, Shuo Zhou, Haikun Zhu, Chung-Kuan Cheng	An Algorithmic Approach for Generic Parallel Adders.	ICCAD	2003	DBLP DOI BibTeX RDF
2	Antonio Blotti, Maurizio Castellucci, Roberto Saletti	Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library.	PATMOS	2002	DBLP DOI BibTeX RDF
2	Radomir S. Stankovic, Jaakko Astola	Some Remarks on Linear Transform of Variables in Representation of Adders by Word-Level Expressions and Spectral Transform Decision Diagrams. (PDF / PS)	ISMVL	2002	DBLP DOI BibTeX RDF	Decision diagrams, Logic design, Switching functions, Spectral transforms
2	Peter Kornerup	Reviewing 4-to-2 Adders for Multi-Operand Addition.	ASAP	2002	DBLP DOI BibTeX RDF
2	Mary D. Brown, Yale N. Patt	Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files.	HPCA	2002	DBLP DOI BibTeX RDF	redundant binary, limited bypass, pipelined register file, signed digit
2	Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan	A New Divide and Conquer Method for Achieving High Speed Division in Hardware.	VLSI Design	2002	DBLP DOI BibTeX RDF	Carry Propagate Adders, Pipelineability, Throughput, Latency, Rounding, Carry Save Adders, Radix, SRT
2	Oscar Gustafsson, Henrik Ohlsson, Lars Wanhammar	Minimum-adder integer multipliers using carry-save adders.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Henrik Eriksson, Per Larsson-Edefors, William P. Marnane	A regular parallel multiplier which utilizes multiple carry-propagate adders.	ISCAS	2001	DBLP DOI BibTeX RDF