Search results for "address generation"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Carlo Galuzzi, Chunyang Gou, Humberto Calderon, Georgi Gaydadjiev, Stamatis Vassiliadis	High-bandwidth Address Generation Unit.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Address generation unit, Stride, Parallel memory
3	Guillermo Talavera, Murali Jayapala, Jordi Carrabina, Francky Catthoor	Address Generation Optimization for Embedded High-Performance Processors: A Survey.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	optimization, embedded, address generation
3	Kuei-Ping Shih, Jang-Ping Sheu, Chih-Yung Chang	Efficient Address Generation for Affine Subscripts in Data-Parallel Programs.	The Journal of Supercomputing	2000	DBLP DOI BibTeX RDF	affine subscripts, multiple induction variables (MIVs), data distribution, distributed-memory multicomputers, single program multiple data (SPMD), data-parallel languages, address generation
2	Humberto Calderon, Carlo Galuzzi, Georgi Gaydadjiev, Stamatis Vassiliadis	High-Bandwidth Address Generation Unit.	SAMOS	2007	DBLP DOI BibTeX RDF
2	André Seznec, Antony Fraboulet	Effective ahead Pipelining of Instruction Block Address Generation. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
2	Deependra Talla, Lizy Kurian John, Doug Burger	Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	bottlenecks in SIMD extensions, hardware address generation, low-overhead looping, superscalar general-purpose processors, performance evaluation, workload characterization, subword parallelism, Media processing, data reorganization
2	J. Ramanujam	Integer Lattice Based Methods for Local Address Generation for Block-Cyclic Distributions.	Compiler Optimizations for Scalable Parallel Systems Languages	2001	DBLP DOI BibTeX RDF
2	Herman Schmit, Donald E. Thomas	Address generation for memories containing multiple arrays.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
2	Miguel Miranda, M. Kaspar, Francky Catthoor, Hugo De Man	Architectural exploration and optimization for counter based hardware address generation.	ED&TC	1997	DBLP DOI BibTeX RDF
2	Miguel Miranda, Francky Catthoor, Martin Janssen, Hugo De Man	ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures. (PDF / PS)	ISSS	1996	DBLP DOI BibTeX RDF
2	Rainer Leupers, Peter Marwedel	Algorithms for address assignment in DSP code generation.	ICCAD	1996	DBLP DOI BibTeX RDF	code generation, address generation
2	Yiannakis Sazeides, Stamatis Vassiliadis, James E. Smith	The Performance Potential of Data Dependence Speculation & Collapsing.	MICRO	1996	DBLP BibTeX RDF	address generation-load dependences, address prediction rate, base instruction level parallel machine, dependence collapsing, performance potential, true data dependences, parallel programming, trace-driven simulation, data dependence speculation, address prediction
2	Herman Schmit, Donald E. Thomas	Address generation for memories containing multiple arrays.	ICCAD	1995	DBLP DOI BibTeX RDF
2	Zhiyong Liu, Xiaobo Li, Jia-Huai You	On storage schemes for parallel array access.	ICS	1992	DBLP DOI BibTeX RDF	matrix manipulation, parallel processing, address generation, skewing schemes, memory conflict
1	Jonghoon Ryu	Efficient Address Generation for Permutation Polynomial Based Interleavers over Integer Rings.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Muhammad Ali Shami, Ahmed Hemani	Address generation scheme for a coarse grain reconfigurable architecture.	ASAP	2011	DBLP DOI BibTeX RDF
1	Cyrille Chavet, Philippe Coussy, Eric Martin, Pascal Urard	Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures	CoRR	2010	DBLP BibTeX RDF
1	Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin	Static Address Generation Easing: a design methodology for parallel interleaver architectures.	ICASSP	2010	DBLP DOI BibTeX RDF
1	Weijia Li, Youtao Zhang	An efficient code update scheme for DSP applications in mobile embedded systems.	LCTES	2010	DBLP DOI BibTeX RDF	context-aware script, context-unaware script, incremental coalescing general offset assignment (icgoa), incremental coalescing simple offset assignment (icsoa)
1	Ittetsu Taniguchi, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Yoshinori Takeuchi, Masaharu Imai	Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Karthik Ramani, Christiaan P. Gribble, Al Davis	StreamRay: a stream filtering architecture for coherent ray tracing.	ASPLOS	2009	DBLP DOI BibTeX RDF	wide simd architectures, ray tracing, graphics processors, interactive rendering
1	Jongmin Lee 0002, Soontae Kim	An energy-delay efficient 2-level data cache architecture for embedded system.	ISLPED	2009	DBLP DOI BibTeX RDF	2-level data cache, early cache hit predictor, one-way write
1	Xin Xiao, Erdal Oruklu, Jafar Saniie	Fast memory addressing scheme for radix-4 FFT implementation.	EIT	2009	DBLP DOI BibTeX RDF
1	Min Li, David Novo, Bruno Bougard, Trevor Carlson, Liesbet Van der Perre, Francky Catthoor	Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures.	IEEE Transactions on Signal Processing	2009	DBLP DOI BibTeX RDF
1	Christos Strydis, Georgi Gaydadjiev	Profiling of lossless-compression algorithms for a novel biomedical-implant architecture.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	implantable devices, microarchitectural profiling, lossless compression, ultra-low power
1	Hesham S. Ali, Hatem M. El-Boghdadi, Samir I. Shaheen	A new heuristic for SOA problem based on effective tie break function.	SCOPES	2008	DBLP DOI BibTeX RDF
1	Hassan Salamy, J. Ramanujam	Storage optimization through code size reduction for digital signal processors.	ESTImedia	2008	DBLP DOI BibTeX RDF
1	Hassan Salamy, J. Ramanujam	Optimal address register allocation for arrays in DSP applications.	ESTImedia	2008	DBLP DOI BibTeX RDF
1	Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong Hu, Zhiping Jia, Weijia Jia, Edwin Hsing-Mean Sha	Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks.	ICASSP	2008	DBLP DOI BibTeX RDF
1	Jarno Vanne, Eero Aho, Timo D. Hämäläinen, Kimmo Kuusilinna	A Parallel Memory System for Variable Block-Size Motion Estimation Algorithms.	IEEE Trans. Circuits Syst. Video Techn.	2008	DBLP DOI BibTeX RDF
1	Joachim Keinert, Christian Haubelt, Jürgen Teich	Synthesis of Multi-dimensional High-Speed FIFOs for Out-of-Order Communication.	ARCS	2008	DBLP DOI BibTeX RDF
1	Han-Xin Sun, Kun-Peng Yang, Yulai Zhao, Dong Tong, Xu Cheng	CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	instruction TLB, instruction fetch unit, power-efficient design, computer architecture, dynamic voltage scaling, instruction cache
1	Jae Hyun Baek, Sung Dae Kim, Myung Hoon Sunwoo	SPOCS: Application Specific Signal Processor for OFDM Communication Systems.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	ASSP, Communications, FFT, DSP, OFDM, Application-Specific Instruction-Set Processor (ASIP), Bit manipulation
1	Ismail Kadayif, Partho Nath, Mahmut T. Kandemir, Anand Sivasubramaniam	Reducing Data TLB Power via Compiler-Directed Address Generation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Jia Wang, Ming-Yang Kao, Hai Zhou	Address generation for nanowire decoders.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	testing, decoder, nanowire
1	Tirath Ramdas, Gregory K. Egan, David Abramson, Kim Baldridge	Converting massive TLP to DLP: a special-purpose processor for molecular orbital computations.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	thread-level parallelism, content-addressable memory, vector processing, address generation, data-level parallelism
1	R. Krishnan, S. Murali Krishna, P. Siva Nandhan	Combinatorial testing: learnings from our experience.	ACM SIGSOFT Software Engineering Notes	2007	DBLP DOI BibTeX RDF	testcase generation, orthogonal arrays, combinatorial testing
1	S. V. Yarmolik, Ireneusz Mrozek, B. Sokol	Address Sequences Generation for Multiple Run Memory Testing.	CISIM	2007	DBLP DOI BibTeX RDF
1	Tsun-Hsien Wang, Ching-Te Chiu	Low Power Design of High Performance Memory Access Architecture for HDTV Decoder.	ICME	2007	DBLP DOI BibTeX RDF
1	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura	A CAM Emulator Using Look-Up Table Cascades.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Rachit Agarwal, Emanuel M. Popovici, Brendan O'Flynn, Michael E. O'Sullivan	A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Zhenmin Li, Taewhan Kim	Address Code Optimization Exploiting Code Scheduling in DSP Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Dan Nicolaescu, Babak Salamat, Alexander V. Veidenbaum	Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy.	ICCD	2006	DBLP BibTeX RDF
1	Tomas Henriksson, Pieter van der Wolf	TTL Hardware Interface: A High-Level Interface for Streaming Multiprocessor Architectures.	ESTImedia	2006	DBLP DOI BibTeX RDF
1	Junho Cho, Hoseok Chang, Wonyong Sung	An FPGA based SIMD processor with a vector memory unit.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Ming-Der Shieh, Tai-Ping Wang, Chien-Ming Wu, Chun-Ming Huang	Efficient path metric access for reducing interconnect overhead in Viterbi decoders.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Hoseok Chang, Junho Cho, Wonyong Sung	Performance Evaluation of an SIMD Architecture with a Multi-bank Vector Memory Unit.	SiPS	2006	DBLP DOI BibTeX RDF
1	Hassan Salamy, J. Ramanujam	An Effective Heuristic for Simple Offset Assignment with Variable Coalescing.	LCPC	2006	DBLP DOI BibTeX RDF
1	Najeem Lawal, Benny Thörnberg, Mattias O'Nils	Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems.	FPL	2005	DBLP BibTeX RDF
1	Chu Chao, Zhang Qin, Xie Yingke, Han Chengde	Design of a high performance FFT processor based on FPGA.	ASP-DAC	2005	DBLP DOI BibTeX RDF	FFT processor, overflow control, FPGA, address generation
1	S. Mayilavelane Aroutchelvame, Kaamran Raahemifar	An Efficient Architecture for Lifting-Based Forward and Inverse Discrete Wavelet Transform.	ICME	2005	DBLP DOI BibTeX RDF	DWT architecture, DWT, Lifting, JPEG 2000
1	Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen	Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	heterogeneous reconfigurable multimedia systems, energy efficiency, reconfigurable computing, discrete wavelet transform, lifting scheme
1	Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere	Solving Out-of-Order Communication in Kahn Process Networks.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	producer/consumer pair, in-order, reordering memory, lower bound, rank function, Kahn Process Network, out-of-order
1	Ismail Kadayif, Partho Nath, Mahmut T. Kandemir, Anand Sivasubramaniam	Compiler-directed physical address generation for reducing dTLB power.	ISPASS	2004	DBLP DOI BibTeX RDF
1	Binu K. Mathew, Al Davis	A loop accelerator for low power embedded VLIW processors.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	embedded systems, low power design, VLIW
1	Chia-Lin Yang, Alvin R. Lebeck, Hung-Wei Tseng, Chien-Hao Lee	Tolerating memory latency through push prefetching for pointer-intensive applications.	TACO	2004	DBLP DOI BibTeX RDF	linked data structures, pointer-chasing, Prefetch, memory hierarchy
1	Sambuddhi Hettiaratchi, Peter Y. K. Cheung	A Novel Implementation of Tile-Based Address Mapping.	DATE	2004	DBLP DOI BibTeX RDF
1	Saad Bouguezel, M. Omair Ahmad, M. N. S. Swamy	An efficient split-radix FHT algorithm.	ISCAS	2004	DBLP DOI BibTeX RDF
1	Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar	Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories.	VLSI Design	2004	DBLP DOI BibTeX RDF	Built-in self-test for memories, neighbourhood pattern sensitive faults, programmable BIST
1	Jian Chen, Ruhao Xu, Yuzhuo Fu	Architecture Design of a High-Performance 32-Bit Fixed-Point DSP.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
1	Bernhard Wess, Thomas Zeitlhofer	On the Phase Coupling Problem Between Data Memory Layout Generation and Address Pointer Assignment.	SCOPES	2004	DBLP DOI BibTeX RDF
1	Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin, Lizy Kurian John	On load latency in low-power caches.	ISLPED	2003	DBLP DOI BibTeX RDF	load latency, low-power, caches
1	Xiaotong Zhuang, ChokSheak Lau, Santosh Pande	Storage assignment optimizations through variable coalescence for embedded processors.	LCTES	2003	DBLP DOI BibTeX RDF	GOA, variable coalescence, SOA, storage assignment
1	Kyung Lan Heo, Sung M. Cho, Jung Hoo Lee, Myung Hoon Sunwoo	Application-Specific DSP Architecture For Fast Fourier Transform.	ASAP	2003	DBLP DOI BibTeX RDF
1	Erik Eckstein, Bernhard Scholz	Addressing Mode Selection.	CGO	2003	DBLP DOI BibTeX RDF
1	Jarmo Takala, Tuomas Järvinen, Harri Sorokin	Conflict-free parallel memory access scheme for FFT processors.	ISCAS	2003	DBLP DOI BibTeX RDF
1	V. V. N. S. Sarvani, R. Govindarajan	Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset Assignment.	SCOPES	2003	DBLP DOI BibTeX RDF
1	Juan C. Moure, Dolores Rexachs, Emilio Luque	Speeding Up Target Address Generation Using a Self-indexed FTB (Research Note).	Euro-Par	2002	DBLP DOI BibTeX RDF
1	Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere	A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks.	ASAP	2002	DBLP DOI BibTeX RDF
1	Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff	Implementation of a Streaming Execution Unit.	DSD	2002	DBLP DOI BibTeX RDF
1	Mohd. Hasan, Tughrul Arslan	A coefficient memory addressing scheme for VLSI implementation of FFT processors.	ISCAS	2002	DBLP DOI BibTeX RDF
1	William N. N. Hung, Xiaoyu Song	On data address computation for embedded DSP systems.	ISCAS	2002	DBLP DOI BibTeX RDF
1	J. Ramanujam, Satish Krishnamurthy, Jinpyo Hong, Mahmut T. Kandemir	Address Code and Arithmetic Optimizations for Embedded Systems.	VLSI Design	2002	DBLP DOI BibTeX RDF	address arithmetic optimization, array access to scalar access conversion, embedded systems, compiler optimizations, pointers
1	Masaki Aida, Tetsuya Abe	Pseudo-Address Generation Algorithm of Packet Destinations for Internet Performance Simulation.	INFOCOM	2001	DBLP BibTeX RDF
1	Preeti Ranjan Panda, Francky Catthoor, Nikil D. Dutt, Koen Danckaert, Erik Brockmeyer, Chidamber Kulkarni, Arnout Vandecappelle, Per Gunnar Kjeldsberg	Data and memory optimization techniques for embedded systems.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	data optimization, memory architecture customization, memory power dissipation, high-level synthesis, survey, SRAM, allocation, data cache, DRAM, register file, architecture exploration, code transformation, address generation, size estimation
1	Markus Lorenz, David Koffmann, Steven Bashford, Rainer Leupers, Peter Marwedel	Optimized address assignment for DSPs with SIMD memory accesses.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Chi-Keung Luk	Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors.	ISCA	2001	DBLP DOI BibTeX RDF
1	Jiyang Kang, Jongbok Lee, Wonyong Sung	A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation.	VLSI Signal Processing	2001	DBLP DOI BibTeX RDF	code converter, compiler-friendly, performance evaluation, digital signal processor, architecture synthesis
1	Chia-Lin Yang, Alvin R. Lebeck	Push vs. pull: data movement for linked data structures.	ICS	2000	DBLP DOI BibTeX RDF
1	Jeffrey Kang, Albert van der Werf, Paul E. R. Lippens	Mapping Array Communication onto FIFO Communication - Towards an Implementation.	ISSS	2000	DBLP DOI BibTeX RDF
1	Song Chen, Adam Postula	Synthesis of custom interleaved memory systems.	IEEE Trans. VLSI Syst.	2000	DBLP DOI BibTeX RDF
1	Amit Rao, Santosh Pande	Storage Assignment Optimizations to Generate Compact and Efficient Code on Embedded DSPs.	PLDI	1999	DBLP DOI BibTeX RDF
1	Song Chen, Adam Postula, Lech Józwiak	Synthesis of XOR Storage Schemes with Different Cost for Minimization of Memory Contention.	EUROMICRO	1999	DBLP DOI BibTeX RDF
1	Ben-Chung Cheng, Daniel A. Connors, Wen-mei W. Hwu	Compiler-Directed Early Load-Address Generation.	MICRO	1998	DBLP BibTeX RDF
1	Kuei-Ping Shih, Jang-Ping Sheu, Chih-Yung Chang	Efficient Address Generation for Affine Subscripts in Data-Parallel Programs. (PDF / PS)	ICPADS	1998	DBLP DOI BibTeX RDF
1	Anupam Basu, Rainer Leupers, Peter Marwedel	Register-Constrained Address Computation in DSP Programs.	DATE	1998	DBLP DOI BibTeX RDF	DSP compiler, address computation, embedded processors
1	Adam Postula, Song Chen, Lech Józwiak, David Abramson	Automated Synthesis of Interleaved Memory Systems for Custom Computing Machine.	EUROMICRO	1998	DBLP DOI BibTeX RDF
1	Nelson L. Passos, Edwin Hsing-Mean Sha	Synthesis of Multi-Dimensional Applications in VHDL. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	Multidimensional Loops, Scheduling, VHDL, Circuit Optimization, Address generation
1	Hangu Yeo, Yu Hen Hu	A Modular Architecture for Real Time HDTV Motion Estimation with Large Search Range.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
1	Kees van Reeuwijk, Will Denissen, Henk J. Sips, Edwin M. R. M. Paalvast	An Implementation Framework for HPF Distributed Arrays on Message-Passing Parallel Computer Systems.	IEEE Trans. Parallel Distrib. Syst.	1996	DBLP DOI BibTeX RDF	message aggregation, parallel computers, message passing, HPF, distributed arrays
1	Ken Kennedy, Nenad Nedeljkovic, Ajay Sethi	Efficient Address Generation for Block-Cyclic Distributions.	International Conference on Supercomputing	1995	DBLP DOI BibTeX RDF
1	H. Pottinger, W. Eatherton, J. Kelly, T. Schiefelbein, L. R. Mullin, R. Ziegler	Hardware Assists for High Performance Computing Using a Mathematics of Arrays.	FPGA	1995	DBLP DOI BibTeX RDF
1	Todd M. Austin, Dionisios N. Pnevmatikatos, Gurindar S. Sohi	Streamlining Data Cache Access with Fast Address Calculation.	ISCA	1995	DBLP DOI BibTeX RDF
1	Uming Ko, T. Balsara, Wai Lee	Low-power design techniques for high-performance CMOS adders.	IEEE Trans. VLSI Syst.	1995	DBLP DOI BibTeX RDF
1	Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh, Albert van der Werf	PHIDEO: High-level synthesis for high throughput applications.	VLSI Signal Processing	1995	DBLP DOI BibTeX RDF
1	Michael Golden, Trevor N. Mudge	A comparison of two pipeline organizations.	MICRO	1994	DBLP DOI BibTeX RDF	pipelines, cache memory, RISC, memory system, interlocks
1	Jos van Sas, Francky Catthoor, Hugo De Man	Test Algorithms for Double-Buffered Random Access and Pointer-Addressed Memories.	IEEE Design & Test of Computers	1993	DBLP DOI BibTeX RDF
1	Kichul Kim, Viktor K. Prasanna	Latin Squares for Parallel Array Access.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	parallel array access, perfect latin squares, skewing functions, self-routing Benes networks, shared memory systems, storage management, multiprocessorinterconnection networks, conflict free access, skewing scheme, parallel memory system
1	Jef L. van Meerbergen, Paul E. R. Lippens, B. T. McSweeney, Wim F. J. Verhaegh, Albert van der Werf, A. van Zanten	Architectural strategies for high-throughput applications.	VLSI Signal Processing	1993	DBLP DOI BibTeX RDF