Search results for "analog"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
7	Bassem A. Alhalabi, Magdy A. Bayoumi	A scalable analog architecture for neural networks with on-chip learning and refreshing.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	analogue storage, scalable analog architecture, on-chip learning, on-chip refreshing, analog storage, analog functional blocks, analog pass switches, system versatility, learning speed, local analog synaptic updating scheme, unbounded scalability, neural networks, learning (artificial intelligence), neural chips, analogue processing circuits
6	Janusz Rzeszut, Bozena Kaminska, Yvon Savaria	A new method for testing mixed analog and digital circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	charge-coupled device circuits, mixed analog and digital circuits, analog test points, simultaneous observation, analog multiplexer, signal path, analog shift register, input voltage, integrated circuit testing, shift registers, mixed analogue-digital integrated circuits, charge coupled device, analogue processing circuits
5	Anirudh Devgan, Bulent Basaran, David Colleran, Mar Hershenson	Accelerated design of analog, mixed-signal circuits in Titan.	ISPD	2009	DBLP DOI BibTeX RDF	analog circuit layout, analog/digital, custom design, layout, physical design, analog circuits, mixed-signal circuits
5	Boris Murmann	Digitally Assisted Analog Circuits.	IEEE Micro	2006	DBLP DOI BibTeX RDF	analog signals, digital computing, analog circuits, analog-to-digital converter
5	Shekhar Y. Borkar, Robert W. Brodersen, Jue-Hsien Chern, Eric Naviasky, D. Saias, Charles Sodini	Tomorrow's analog: just dead or just different?	DAC	2006	DBLP DOI BibTeX RDF	analog CAD tools, analog design methodologies, mixed-signal design, analog design, RF design
5	Yvan Maidon, Thomas Zimmer, André Ivanov	An Analog Circuit Fault Characterization Methodology.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	analog circuit testing, analog fault diagnosis, analog fault characterization
5	Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi	Correct-by-construction layout-centric retargeting of large analog designs.	DAC	2004	DBLP DOI BibTeX RDF	analog integrated circuit design, analog layout automation, analog synthesis and optimization, layout symmetry
5	Saied Hemati, Amir H. Banihashemi	Iterative decoding in analog CMOS.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	analog CMOS, analog iterative decoder, asynchronous iterative decoding, min-sum decoding, soft decoding, analog circuit, turbo codes, iterative decoding, low-density parity-check codes
5	Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	Ultimate low cost analog BIST.	DAC	2003	DBLP DOI BibTeX RDF	DSP-based analog test, low cost analog BIST, test of analog circuits
5	Salvador Mir, Marcelo Lubaszewski, Bernard Courtois	Unified built-in self-test for fully differential analog circuits.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	on-line/off-line analog test, unified BIST, fully differential analog circuits, common-mode feedback, analog BIST
5	Alexandre R. S. Romariz, P. U. A. Ferreira, J. V. Campêlo Jr., M. L. Graciano Jr., J. C. da Costa	Design of a Hybrid Digital-Analog Neural Co-Processor for Signal Processing.	EUROMICRO	1996	DBLP DOI BibTeX RDF	hybrid digital-analog neural co-processor, digitally-controlled multiplexing, CMOS analog circuits, VLSI, signal processing, VLSI design, multilayer perceptrons, VLSI implementation, hybrid architecture, capacitors, analog multipliers
5	Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham	Efficient multisine testing of analog circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	waveform analysis, biquadratic filters, multisine testing, test waveform generation, test confidence, fault-based automatic test pattern generator, successive gradient method, sinusoidal signals, fault coverage maximization, biquadratic filter, AC testing, analog IC, fault diagnosis, built-in self test, integrated circuit testing, automatic testing, analog circuits, built-in test, analogue integrated circuits, linear analog circuits
4	Bo Liu, Francisco V. Fernández, Georges G. E. Gielen, R. Castro-López, Elisenda Roca	A memetic approach to the automatic design of high-performance analog integrated circuits.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Analog circuit sizing, analog design automation, constrained optimization, memetic algorithm
4	Hugo de Lemos Haas, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia	Analog hardware implementation of a vector quantizer for focal-plane image compression.	SBCCI	2008	DBLP DOI BibTeX RDF	CMOS analog hardware, analog image processing, vector quantization
4	Hugo de Lemos Haas, José Gabriel Rodríguez Carneiro Gomes, Antonio Petraglia	Viability of analog inner product operations in CMOS imagers.	SBCCI	2007	DBLP DOI BibTeX RDF	CMOS analog hardware, analog image processing, vector quantization
4	Amir Zjajo, José Pineda de Gyvez, Guido Gronthoud	Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	structural fault modeling, analog fault modeling, Neyman-Pearson decision, fault detection, analog test, supply current monitoring
4	Michel Morneau, Abdelhakim Khouas	TBSA: Threshold-Based Simulation Accuracy Method for Fast Analog DC Fault Simulation.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	DC fault simulation, analog fault detection, Newton-Raphson algorithm, analog testing
4	Miguel Angel Domínguez, José L. Ausín, J. Francisco Duque-Carrillo, Guido Torelli	A 1-MHz Area-Efficient On-Chip Spectrum Analyzer for Analog Testing.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	analog built-in self-test, analog IC test, on-chip spectrum analyzer, switched-capacitor circuits, non-uniform sampling
4	Jonathan W. Mills, Matt Parker, Bryce Himebaugh, Craig Shue, Brian Kopecky, Chris Weilemann	"Empty space" computes: the evolution of an unconventional supercomputer.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	Lukasiewicz logic, extended analog computer, general purpose analog computer, hybrid digital-analog architecture
4	Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey	A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm2 Segmented Current Steering CMOS DAC.	VLSI Design	2005	DBLP DOI BibTeX RDF	MOS Analog Circuits, Digital to Analog Conversion, Mixed Analog -Digital Integrated Circuits, Low Power
4	Haralampos-G. D. Stratigopoulos, Yiorgos Makris	An Analog Checker with Input-Relative Tolerance for Duplicate Signals.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	analog checkers, on-line test, analog test, concurrent test
4	Eric E. Fabris, Luigi Carro, Sergio Bampi	Modeling and designing high performance analog reconfigurable circuits.	SBCCI	2004	DBLP DOI BibTeX RDF	analog programmability, band-pass sigma-delta modulator, analog design, FPAA
4	Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou	Intrinsic response for analog module testing using an analog testability bus.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	analog testability bus, intrinsic response, design for testability, analog testing, boundary scan
4	Farzan Aminian, Mehran Aminian	Fault Diagnosis of Analog Circuits Using Bayesian Neural Networks with Wavelet Transform as Preprocessor.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	analog fault diagnosis, Bayesiasn learning, neural networks, analog circuits
4	Alvernon Walker, Parag K. Lala	A Transition Based BIST Approach for Passive Analog Circuits.	ISQED	2000	DBLP DOI BibTeX RDF	Built-in Self Test, Analog Test, Analog BIST, Mixed-Signal BIST
4	Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell	TI-BIST: a temperature independent analog BIST for switched-capacitor filters.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	temperature independent analog BIST, simulation, built-in self test, BIST, analogue circuits, switched capacitor filters, switched-capacitor filters, analog BIST
4	Matthew Worsman, Mike W. T. Wong, Y. S. Lee	Analog circuit equivalent faults in the D.C. domain.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	analog circuit faults, fault simulation data, equivalent faults, equivalent fault identification, built-in self test, design for testability, data analysis, fault simulation, fault location, fault location, analogue circuits, linear analog circuits
4	Chauchin Su, Yue-Tsang Chen	Crosstalk Effect Removal for Analog Measurement in Analog Test Bus.	VTS	2000	DBLP DOI BibTeX RDF	Analog Test Bus, Design for Testability, Analog Test, Mixed Signal Test
4	Jan Arild Tofte, Chee-Kian Ong, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng	Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test.	VTS	2000	DBLP DOI BibTeX RDF	cross-correlation signature register, CCSR, implicit functional testing, harmonic distortion, THD, classification, synthesis, noise, BIST, convex hull, polygon, discrimination, analog test, cross-correlation, mixed-signal, pseudo-random, pseudo-random, labview, impulse response, performance parameter, analog BIST
4	Anna Maria Brosa, Joan Figueras	Characterization of Floating Gate Defects in Analog Cells.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	floating gate defect, low-power/low-voltage analog circuits, analog testing
4	Ramakrishna Voorakaranam, Abhijit Chatterjee	Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test.	ARVLSI	1999	DBLP DOI BibTeX RDF	analog verification, fault diagnosis, test generation, analog testing, Backtrace
4	G. Droege, M. Thole, Ernst-Helmut Horneber	EASY - a System for Computer-Aided Examination of Analog Circuits.	DATE	1998	DBLP DOI BibTeX RDF	analog design system, computer-aided design, analog circuits, symbolic analysis, qualitative analysis
4	Chanchal Chatterjee, Vwani P. Roychowdhury	An efficient contrast-enhancement method using the analog to digital converter.	Mach. Vis. Appl.	1996	DBLP DOI BibTeX RDF	Analog enhancement, Analog to digital converter
4	Salvador Mir, Marcelo Lubaszewski, Bernard Courtois	Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	analog ATPG, fault diagnosis, fault-based testing, analog BIST
4	Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting	Metrology for analog module testing using analog testability bus.	ICCAD	1996	DBLP DOI BibTeX RDF	analog module, analog module testing, multiple instantiation, test response analysis, test waveform, testability bus, design for testability
4	Bogdan G. Arsintescu	A Method for Analog Circuits Visualization. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	Analog circuits visualization, Design verification tools, Computer aided design for analog circuits
4	Rajesh Ramadoss, Michael L. Bushnell	Test generation for mixed-signal devices using signal flow graphs.	VLSI Design	1996	DBLP DOI BibTeX RDF	mixed-signal devices, reverse simulation approach, component tolerances, analog input sinusoids, test generation results, analog backtrace method, high-order analog circuits, fault diagnosis, test generation, integrated circuit testing, automatic testing, circuit analysis computing, mixed analogue-digital integrated circuits, signal flow graphs, signal flow graphs, nonlinear circuits
4	Michel Renovell, Florence Azaïs, Yves Bertrand	A design-for-test technique for multistage analog circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	design-for-test technique, multistage analog circuits, DFT approach, op-amp-based modules, testability resources, transparent paths, external I/O, local I/O, test mode, on-chip digital resources, analog response penalty, controllability, controllability, integrated circuit testing, design for testability, observability, observability, mixed-signal circuits, mixed analogue-digital integrated circuits, test management, production testing
4	Stephen K. Sunter	A low cost 100 MHz analog test bus.	VTS	1995	DBLP DOI BibTeX RDF	analog test bus, on-chip analog bus, digital three-state inverter, low-input capacitance, signal bandwidth, bus input, design for testability, DFT, integrated circuit design, mixed-signal circuits, capacitance, mixed analogue-digital integrated circuits, IC design, 100 MHz
4	Anirudh Devgan, Ronald A. Rohrer	Efficient simulation of interconnect and mixed analog-digital circuits in ACES.	VLSI Design	1995	DBLP DOI BibTeX RDF	adaptively controlled explicit simulation, mixed analog-digital circuits, analog circuit simulation, interconnect circuit simulation, AWE macromodels, nonlinear terminations, variable accuracy device models, circuit topology constraints removal, timing, circuit analysis computing, transient analysis, analogue integrated circuits, integrated circuit interconnections, mixed analogue-digital integrated circuits, ACES, transient simulation, timing simulation
4	Jan Crols, Stéphane Donnay, Michiel Steyaert, Georges G. E. Gielen	A high-level design and optimization tool for analog RF receiver front-ends.	ICCAD	1995	DBLP DOI BibTeX RDF	analog CAD, analog high-level synthesis, RF design and optimization
3	Qiang Gao, Yin Shen, Yici Cai, Hailong Yao	Analog circuit shielding routing algorithm based on net classification.	ISLPED	2010	DBLP DOI BibTeX RDF	analog routing, shielding routing, A* algorithm
3	Janardhanan S. Ajit, Yong-Bin Kim, Minsu Choi	Performance assessment of analog circuits with carbon nanotube FET (CNFET).	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	analog, circuits
3	Michael Eick, Martin Strasser, Helmut E. Graeb, Ulf Schlichtmann	Automatic generation of hierarchical placement rules for analog integrated circuits.	ISPD	2010	DBLP DOI BibTeX RDF	hierarchical placement rules, constraints, placement, analog integrated circuits
3	Mar Hershenson	Design platform for electrical and physical co-design of analog circuits.	ISPD	2010	DBLP DOI BibTeX RDF	design, analog, co-design
3	Rob A. Rutenbar	Analog layout synthesis: what's missing?	ISPD	2010	DBLP DOI BibTeX RDF	synthesis, layout, analog
3	Bradley N. Bond, Luca Daniel	Automated compact dynamical modeling: an enabling tool for analog designers.	DAC	2010	DBLP DOI BibTeX RDF	parameterized modeling, semidefinite programming, model reduction, analog design, compact modeling
3	Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang	Performance-driven analog placement considering boundary constraint.	DAC	2010	DBLP DOI BibTeX RDF	analog placement, boundary constraint, symmetry
3	Mark Horowitz, Metha Jeeradit, Frances Lau, Sabrina Liao, ByongChan Lim, James Mao	Fortifying analog models with equivalence checking and coverage analysis.	DAC	2010	DBLP DOI BibTeX RDF	analog validation, model-first design, design methodology, fault coverage, equivalence checking, formal validation
3	Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu	Behavior-level yield enhancement approach for large-scaled analog circuits.	DAC	2010	DBLP DOI BibTeX RDF	process variation, analog circuits, yield enhancement
3	Brandon Rumberg, David W. Graham, Vinod Kulathumani	Hibernets: energy-efficient sensor networks using analog signal processing.	IPSN	2010	DBLP DOI BibTeX RDF	analog signal processing, selective wake up, sensor networks, energy-efficient, in-network processing
3	Brandon Rumberg, David W. Graham, Vinod Kulathumani	Hibernets: energy-efficient sensor networks using analog signal processing.	IPSN	2010	DBLP DOI BibTeX RDF	analog signal processing, selective wake up, sensor networks, energy-efficient, in-network processing
3	Moshe Mishali, Yonina C. Eldar	Xampling: Analog Data Compression.	DCC	2010	DBLP DOI BibTeX RDF	analog processing circuits, data conversion, sampling methods, analog digital conversion
3	Jérôme Durand-Lose	Abstract geometrical computation 3: black holes for classical and analog computing.	Natural Computing	2009	DBLP DOI BibTeX RDF	Black hole model, Malament-Hogarth space-time, Hyper-computing, Zeno phenomenon, Analog computation, Arithmetic hierarchy, Abstract geometrical computation
3	Jernej Olensek, Árpád Bürmen, Janez Puhan, Tadej Tuma	DESA: a new hybrid global optimization method and its application to analog integrated circuit sizing.	J. Global Optimization	2009	DBLP DOI BibTeX RDF	Analog integrated circuit sizing, Optimization, Simulated annealing, Differential evolution
3	Pedro Sousa, Carla Duarte, Nuno Horta	FUGA: a fuzzy-genetic analog circuit optimization kernel.	GECCO	2009	DBLP DOI BibTeX RDF	genetic algorithms, optimization, CAD, analog circuit, fuzzy model
3	Meng-Hui Wang, Yu-Kuo Chung, Wen-Tsai Sung	The Fault Diagnosis of Analog Circuits Based on Extension Theory.	ICIC	2009	DBLP DOI BibTeX RDF	Extension theory (ET), Fault diagnosis, Analog circuit
3	Luciano A. de Lacerda, Edson P. Santana, Cleber Vinícius A. de Almeida, Ana Isabela A. Cunha	Distortion analysis of analog multiplier circuits using two-dimensional integral nonlinear function.	SBCCI	2009	DBLP DOI BibTeX RDF	CMOS multipliers, distortion, analog multipliers
3	Wimol San-Um, Masayoshi Tachibana	Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits.	SBCCI	2009	DBLP DOI BibTeX RDF	impulse stimulation, linear analog integrated circuits, response sampling technique, built-in self test
3	Zhihong Feng, Zhigui Lin, Wei Fang, Wei Wang, Zhitao Xiao	Analog Circuit Fault Fusion Diagnosis Method Based on Support Vector Machine.	ISNN	2009	DBLP DOI BibTeX RDF	Multi- classification, Support Vector Machine, Fault diagnosis, Analog circuit
3	Yigang He, Wenji Zhu	Fault Diagnosis of Nonlinear Analog Circuits Using Neural Networks and Multi-Space Transformations.	ISNN	2009	DBLP DOI BibTeX RDF	Bilinear Transformation, Space Transformation, Neural Network, Fault Diagnosis, Analog Circuits
3	Eric Soenen	Physical design methodology for analog circuitsin a system-on-a-chip environment.	ISPD	2009	DBLP DOI BibTeX RDF	analog design automation
3	Göran Jerke, Jens Lienig	Constraint-driven design: the next step towards analog design automation.	ISPD	2009	DBLP DOI BibTeX RDF	constraint-driven design, constraints, layout, physical design, analog design
3	Masashi Kawaguchi, Shoji Suzuki, Takashi Jimbo, Naohiro Ishii	Speed Flexibility Biomedical Vision Model Using Analog Electronic Circuits and VLSI Layout Design.	KES	2009	DBLP DOI BibTeX RDF	Biomedical Vision System, Neural Network, Motion Detection, Analog Circuits
3	Gabriel Oltean, Sorin Hintea, Emilia Sipos	A Genetic Algorithm-Based Multiobjective Optimization for Analog Circuit Design.	KES	2009	DBLP DOI BibTeX RDF	Pareto ranking, genetic algorithm, multiobjective optimization, Pareto front, analog circuit design
3	Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang	Thermal-driven analog placement considering device matching.	DAC	2009	DBLP DOI BibTeX RDF	analog placement, thermal matching
3	Xuening Sun, Pierluigi Nuzzo, Chang-Ching Wu, Alberto L. Sangiovanni-Vincentelli	Contract-based system-level composition of analog circuits.	DAC	2009	DBLP DOI BibTeX RDF	integration, composition, contract, system, analog, UWB, platform, platform-based design, radio-frequency, assume-guarantee
3	Tomonori Shirotori, Yuko Osana	Improved Kohonen Feature Map Associative Memory with Area Representation for Sequential Analog Patterns.	ICANN	2009	DBLP DOI BibTeX RDF	Kohonen Feature Map (Self-Organizing Map), Successive Learning, Sequential Analog Pattern, Associative Memory
3	Corneliu Rusu, Lacrimioara Grama, Jarmo Takala	SPICE Simulation of Analog Filters: A Method for Designing Digital Filters.	EUROCAST	2009	DBLP DOI BibTeX RDF	analog filter, SPICE, digital filter
3	Jaeha Kim	Mixed-Signal System Verification: A High-Speed Link Example.	CAV	2009	DBLP DOI BibTeX RDF	analog and mixed-signal verification, analog design intent, linear system models
3	Fang Liu, Sule Ozev, Plamen K. Nikolov	Parametric variability analysis for multistage analog circuits using analytical sensitivity modeling.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Hierarchical variance analysis, parameter correlations, performance model, process variations, analog circuits
3	Yukiya Miura, Jiro Kato	Adaptive Fault Diagnosis of Analog Circuits by Operation-Region Model and X - Y Zoning Method.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	MOS transistors, Fault diagnosis, Analog circuits, Adaptive test
3	Shubhankar Basu, Balaji Kommineni, Ranga Vemuri	Variation Aware Spline Center and Range Modeling for Analog Circuit Performance.	ISQED	2008	DBLP DOI BibTeX RDF	Center and Range, Process Variation, Analog, Spline
3	Saurabh Sinha, Asha Balijepalli, Yu Cao	A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design.	ISQED	2008	DBLP DOI BibTeX RDF	Schottky barrier, analog design metrics, modeling, CNT
3	Laurent Gatet, Hélène Tap-Béteille, Daniel Roviras, Francis Gizard	Integrated CMOS Analog Neural Network Ability to Linearize the Distorted Characteristic of HPA Embedded in Satellites.	DELTA	2008	DBLP DOI BibTeX RDF	CMOS Analog Integrated Circuits, Nonlinear Distortion, Predistorsion, Multi-Layer Perceptrons, Neural Network Architecture
3	Tony Poitschke, Markus Ablaßmeier, Gerhard Rigoll, Stanislavs Bardins, Stefan Kohlbecher, Erich Schneider	Contact-analog information representation in an automotive head-up display.	ETRA	2008	DBLP DOI BibTeX RDF	HUD, contact-analog, eye tracking, calibration, automotive, head-up display
3	Shukai Duan, Lidan Wang	Circuitry Analog and Synchronization of Hyperchaotic Neuron Model.	ISNN	2008	DBLP DOI BibTeX RDF	Chaotic neuron model, circuitry analog, chaos synchronization, adaptive chaos synchronization
3	K. R. Anne, S. K. Bhagavatula, Jean Chamberlain Chedjou, Kyandoghere Kyamakya	Self-organized supply chain networks: theory in practice and an analog simulation based approach.	Autonomics	2008	DBLP DOI BibTeX RDF	adaptive supply chains, analog simulation, self-organized supply chains, supply chain optimization
3	Masashi Kawaguchi, Takashi Jimbo, Naohiro Ishii	Analog VLSI Layout Design and the Circuit Board Manufacturing of Advanced Image Processing for Artificial Vision Model.	KES	2008	DBLP DOI BibTeX RDF	Biomedical Vision System, Neural Network, Motion Detection, Analog Circuits
3	Emilia Sipos, Lelia Festila, Gabriel Oltean	Towards Reconfigurable Circuits Based on Ternary Controlled Analog Multiplexers/Demultiplexers.	KES	2008	DBLP DOI BibTeX RDF	Analog multiplexer, reconfigurable circuit, transmission gate, CMOS transistors, SUS-LOC
3	Gabriel Oltean, Sorin Hintea, Emilia Sipos	Computational Intelligence in Analog Circuits Design.	KES	2008	DBLP DOI BibTeX RDF	genetic algorithm, optimization, fuzzy sets, neuro-fuzzy systems, analog circuit design
3	Mark Po-Hung Lin, Shyh-Chang Lin	Analog placement based on hierarchical module clustering.	DAC	2008	DBLP DOI BibTeX RDF	analog placement, floorplanning
3	Daeik D. Kim, Choongyeun Cho, Jonghae Kim	Analog parallelism in ring-based VCOs.	DAC	2008	DBLP DOI BibTeX RDF	analog parallelism, clock period jitter, process-induced variation, ring-based voltage-controlled oscillator, microprocessor, phase-locked loop, phase noise
3	Kazuki Akutagawa, Kazuya Machida, Takao Waho	A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter.	ISMVL	2008	DBLP DOI BibTeX RDF	algorithmic, redundancy, analog-to-digital converter, multiple-valued
3	Didier Keymeulen, Adrian Stoica, Ricardo Salem Zebulum, Srinivas Katkoori, Pradeep Fernando, Hariharan Sankaran, Mohammad M. Mojarradi, Taher Daud	Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core.	ICES	2008	DBLP DOI BibTeX RDF	Self-Healing and Compensation, Self-reconfigurable, Field Programmable Analog Array
3	Yalin Evren Sagduyu, Dongning Guo, Randall Berry	Throughput and stability of digital and analog network coding for wireless networks with single and multiple relays.	WICON	2008	DBLP DOI BibTeX RDF	analog network coding, digital network coding, queue stability, stable throughput region, throughput optimal control
3	Olga Goussevskaia, Roger Wattenhofer	Complexity of scheduling with analog network coding.	FOWANC	2008	DBLP DOI BibTeX RDF	analog network coding, geometric sinr, physical interference model, scheduling, complexity, np-complete, wireless ad-hoc networks
3	Jorge Oliveros, Dwight Cabrera, Elkim Roa, Wilhelmus A. M. Van Noije	An improved and automated design tool for the optimization of CMOS OTAs using geometric programming.	SBCCI	2008	DBLP DOI BibTeX RDF	OTA design, analog CAD, analog circuit optimization, design methodologies, geometric programming
3	DongHyun Ko, Ji-Hoon Jung, YoungGun Pu, Sang-Kyung Sung, Kang-Yoon Lee, Chul Nam	A Design of 14-bits ADC and DAC for CODEC Applications in 0.18 µm CMOS Process.	DELTA	2008	DBLP DOI BibTeX RDF	ADC(Analog-to-Digital Converter), DAC (Digital-to-Analog Converter), Sigma-Delta Modulator
3	Tathagato Rai Dastidar, P. P. Chakrabarti	A verification system for transient response of analog circuits.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Ana CTL, model checking, query language, Analog circuits, equivalence checking, transient response
3	Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell	Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	Analog built-in self-test, Transient response analysis, FPAA
3	M. A. El-Gamal, M. D. A. Mohamed	Ensembles of Neural Networks for Fault Diagnosis in Analog Circuits.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	fault simulation, boosting, ensemble learning, analog circuits, bagging, fault classification
3	Yaser M. A. Khalifa, Badar K. Khan, Faisal Taha	Multi-objective optimization tool for a free structure analog circuits design using genetic algorithms and incorporating parasitics.	GECCO (Companion)	2007	DBLP DOI BibTeX RDF	genetic algorithms, optimization, analog circuits
3	Nuno C. Lourenço, Nuno C. G. Horta	Automatic analog IC layout generation based on a evolutionary computation approach.	GECCO	2007	DBLP DOI BibTeX RDF	analog ICs, layout generation, evolutionary computation
3	Min Jiang, Zhenkun Yang, Zhaohui Gan	Optimal Components Selection for Analog Active Filters Using Clonal Selection Algorithms.	ICIC	2007	DBLP DOI BibTeX RDF	Analog active filter, Butterworth approximation, Clonal selection algorithms, Components selection
3	Zhenhua Wang	Adaptive analog biasing: a robustness-enhanced low-power technique for analog baseband design.	ISLPED	2007	DBLP DOI BibTeX RDF	robustness enhancement, sensitivity reduction, low-power, low-energy, analog integrated circuits, biasing
3	A. A. Mariano, B. Boumballa, Dominique Dallet, Yann Deval, Jean-Baptiste Begueret	High-speed CMOS analog-to-digital converter for front-end receiver applications.	SBCCI	2007	DBLP DOI BibTeX RDF	flash structure, analog-to-digital converter, data-conversion
3	Fernando da Rocha Paixão Cortes, Sergio Bampi	A fully integrated CMOS RF front-end for a multi-band analog mixed-signal interface.	SBCCI	2007	DBLP DOI BibTeX RDF	RF front-end, VGA, analog/RF design, frequency translation, mixer
3	Manuel F. M. Barros, Jorge Guilherme, Nuno Horta	GA-SVM feasibility model and optimization kernel applied to analog IC design automation.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	analog integrated circuit synthesis, genetic algorithms, support vector machines
3	Raffaella Gentilini, Klaus Schneider, Alexander Dreyer	Three-valued automated reasoning on analog properties.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	(multi valued) temporal logics & model checking, interval arithmetic, analog circuits