Search results for "analog circuits"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham	Efficient multisine testing of analog circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	waveform analysis, biquadratic filters, multisine testing, test waveform generation, test confidence, fault-based automatic test pattern generator, successive gradient method, sinusoidal signals, fault coverage maximization, biquadratic filter, AC testing, analog IC, fault diagnosis, built-in self test, integrated circuit testing, automatic testing, analog circuits, built-in test, analogue integrated circuits, linear analog circuits
3	Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu	Behavior-level yield enhancement approach for large-scaled analog circuits.	DAC	2010	DBLP DOI BibTeX RDF	process variation, analog circuits, yield enhancement
3	Yigang He, Wenji Zhu	Fault Diagnosis of Nonlinear Analog Circuits Using Neural Networks and Multi-Space Transformations.	ISNN	2009	DBLP DOI BibTeX RDF	Bilinear Transformation, Space Transformation, Neural Network, Fault Diagnosis, Analog Circuits
3	Fang Liu, Sule Ozev, Plamen K. Nikolov	Parametric variability analysis for multistage analog circuits using analytical sensitivity modeling.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Hierarchical variance analysis, parameter correlations, performance model, process variations, analog circuits
3	Yukiya Miura, Jiro Kato	Adaptive Fault Diagnosis of Analog Circuits by Operation-Region Model and X - Y Zoning Method.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	MOS transistors, Fault diagnosis, Analog circuits, Adaptive test
3	Tathagato Rai Dastidar, P. P. Chakrabarti	A verification system for transient response of analog circuits.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Ana CTL, model checking, query language, Analog circuits, equivalence checking, transient response
3	Boris Murmann	Digitally Assisted Analog Circuits.	IEEE Micro	2006	DBLP DOI BibTeX RDF	analog signals, digital computing, analog circuits, analog-to-digital converter
3	Yukiya Miura	Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and X-Y Zoning Method: Case Study.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	MOS transistors, operation-region model, X-Y zoning method, fault diagnosis, analog circuits
3	M. A. El-Gamal	Genetically Evolved Neural Networks for Fault Classification in Analog Circuits.	Neural Computing and Applications	2002	DBLP DOI BibTeX RDF	Fault grouping, Genetically evolved neural networks, Genetic algorithms, Fault simulation, Analog circuits, Fault classification
3	Suresh Seshadri, Jacob A. Abraham	Frequency Response Verification of Analog Circuits Using Global Optimization Techniques.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	modeling, verification, global optimization, analog circuits, formal techniques, parameter variation, frequency response
3	Sasikumar Cherubal, Abhijit Chatterjee	Test generation for fault isolation in analog circuits using behavioral models.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	multiple parameter variations, manufacturing tolerances, test generation, fault location, behavioral models, analog circuits, analogue integrated circuits, fault isolation, circuit testing, behavioral descriptions, parametric failures, measurement noise
3	Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen	Fault diagnosis for linear analog circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	discrete signal flow graph, equivalent faults, fault diagnosis, fault diagnosis, signal flow graphs, analogue circuits, linear analog circuits
3	Prakash Gopalakrishnan, Vinita Vasudevan	A Modified Line Expansion Algorithm for Device-level Routing of Analog Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF	routing, layout, analog circuits
3	Lars Hedrich, Erich Barke	A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances.	DATE	1998	DBLP DOI BibTeX RDF	electronic design automation circuit simulation, formal verification, analog circuits
3	Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi	Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling.	VTS	1997	DBLP DOI BibTeX RDF	digital-compatible BIST scheme, pulse response sampling, low-cost BIST scheme, built-in self test scheme, rectangular pulses, digital linear feedback shift register, transient testing, synchronization circuitry, comparison circuitry, BIST hardware design, built-in self test, analog circuits
3	Pramodchandran N. Variyam, Abhijit Chatterjee	Test generation for comprehensive testing of linear analog circuits using transient response sampling.	ICCAD	1997	DBLP DOI BibTeX RDF	Implicit functional testing, Transient testing, Linear Analog Circuits
3	Salvador Mir, Marcelo Lubaszewski, Bernard Courtois	Unified built-in self-test for fully differential analog circuits.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	on-line/off-line analog test, unified BIST, fully differential analog circuits, common-mode feedback, analog BIST
3	Tao Wei, Mike W. T. Wong, Y. S. Lee	Efficient Multifrequency Analysis of Fault Diagnosis in Analog Circuits Based on Large Change Sensitivity Computation.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	large change sensitivity, fault diagnosis, analog circuits
3	Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham	A novel test generation approach for parametric faults in linear analog circuits .	VTS	1996	DBLP DOI BibTeX RDF	digital test software, time-domain tests, equivalent digital circuit, digital test vectors, test waveform, VLSI, test generation, integrated circuit testing, fault location, stuck-at faults, analogue integrated circuits, parametric faults, linear analog circuits, time-domain analysis, equivalent circuits, analogue processing circuits
3	Chen-Yang Pan, Kwang-Ting Cheng	Implicit functional testing for analog circuits.	VTS	1996	DBLP DOI BibTeX RDF	implicit functional testing, linear time-invariant circuits, impulse response samples, pseudo-random technique, production testing time, yield coverages, VLSI, integrated circuit testing, fault coverage, analog circuits, analogue integrated circuits, mixed analogue-digital integrated circuits, transient response
3	Michel Renovell, Florence Azaïs, Yves Bertrand	The multi-configuration: A DFT technique for analog circuits.	VTS	1996	DBLP DOI BibTeX RDF	multi-configuration technique, diagnosis facilities, 8/sup th/ order band pass filter, integrated circuit testing, design for testability, integrated circuit design, analog circuits, analogue integrated circuits, band-pass filters, DFT technique
3	Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi	Low-cost DC built-in self-test of linear analog circuits using checksums.	VLSI Design	1996	DBLP DOI BibTeX RDF	DC built-in self-test, catastrophic failures, line opens, DC transfer function, on-chip fault detection, BIST circuitry, fault diagnosis, built-in self test, integrated circuit testing, transfer functions, analogue integrated circuits, checksums, linear analog circuits, matrix representations, fault classes
3	Bogdan G. Arsintescu	A Method for Analog Circuits Visualization. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	Analog circuits visualization, Design verification tools, Computer aided design for analog circuits
3	Yeong-Ruey Shieh, Cheng-Wen Wu	DC control and observation structures for analog circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	level-sensitive scan-design, test points, DC voltage levels, diagnosis capability, calibration process, read-out voltage levels, VLSI, VLSI, fault diagnosis, controllability, controllability, integrated circuit testing, calibration, observability, observability, analog circuits, mixed signal circuits, mixed analogue-digital integrated circuits
2	Janardhanan S. Ajit, Yong-Bin Kim, Minsu Choi	Performance assessment of analog circuits with carbon nanotube FET (CNFET).	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	analog, circuits
2	Mar Hershenson	Design platform for electrical and physical co-design of analog circuits.	ISPD	2010	DBLP DOI BibTeX RDF	design, analog, co-design
2	Timothée Levi, Jean Tomas, Noëlle Lewis, Pascal Fouillat	A CMOS Resizing Methodology for Analog Circuits.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
2	Meng-Hui Wang, Yu-Kuo Chung, Wen-Tsai Sung	The Fault Diagnosis of Analog Circuits Based on Extension Theory.	ICIC	2009	DBLP DOI BibTeX RDF	Extension theory (ET), Fault diagnosis, Analog circuit
2	Suraj Sindia, Virendra Singh, Vishwani D. Agrawal	Polynomial coefficient based DC testing of non-linear analog circuits.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	DC test, non-linear circuit test, polynomial, curve fitting, parametric faults
2	Kyung-Joong Kim, Sung-Bae Cho	Combining Multiple Evolved Analog Circuits for Robust Evolvable Hardware.	IDEAL	2009	DBLP DOI BibTeX RDF
2	Shubhankar Basu, Balaji Kommineni, Ranga Vemuri	Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space.	VLSI Design	2009	DBLP DOI BibTeX RDF
2	Almitra Pradhan, Ranga Vemuri	Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits.	VLSI Design	2009	DBLP DOI BibTeX RDF
2	Georges G. E. Gielen	Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS.	DDECS	2009	DBLP DOI BibTeX RDF
2	Anirudh Devgan, Bulent Basaran, David Colleran, Mar Hershenson	Accelerated design of analog, mixed-signal circuits in Titan.	ISPD	2009	DBLP DOI BibTeX RDF	analog circuit layout, analog/digital, custom design, layout, physical design, analog circuits, mixed-signal circuits
2	Dana Angluin, James Aspnes, Jiang Chen, Lev Reyzin	Learning large-alphabet and analog circuits with value injection queries.	Machine Learning	2008	DBLP DOI BibTeX RDF	Value injection queries, Learning circuits, Query learning
2	Ying Wei, Alex Doboli	Structural Macromodeling of Analog Circuits Through Model Decoupling and Transformation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Gabriel Oltean, Sorin Hintea, Emilia Sipos	Computational Intelligence in Analog Circuits Design.	KES	2008	DBLP DOI BibTeX RDF	genetic algorithm, optimization, fuzzy sets, neuro-fuzzy systems, analog circuit design
2	Boris Murmann, Christian Vogel, Heinz Koeppl	Digitally enhanced analog circuits: System aspects.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Amal Kumar Kundu, I. Kharagpur, Tathagato Rai Dastidar, Tarun Kanti Bhattacharyya, Partha Ray	A methodology for efficient design of analog circuits using an automated simulation based synthesis tool.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Yukiya Miura, Jiro Kato	Diagnosis of Analog Circuits by Using Multiple Transistors and Data Sampling.	DFT	2008	DBLP DOI BibTeX RDF
2	Chenjie Gu, Jaijeet S. Roychowdhury	Model reduction via projection onto nonlinear manifolds, with applications to analog circuits and biochemical systems.	ICCAD	2008	DBLP DOI BibTeX RDF
2	Ender Yilmaz, Sule Ozev	Dynamic test scheduling for analog circuits for improved test quality.	ICCD	2008	DBLP DOI BibTeX RDF
2	Fang Liu, Sule Ozev	Statistical Test Development for Analog Circuits Under High Process Variations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	M. A. El-Gamal, M. D. A. Mohamed	Ensembles of Neural Networks for Fault Diagnosis in Analog Circuits.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	fault simulation, boosting, ensemble learning, analog circuits, bagging, fault classification
2	Yaser M. A. Khalifa, Badar K. Khan, Faisal Taha	Multi-objective optimization tool for a free structure analog circuits design using genetic algorithms and incorporating parasitics.	GECCO (Companion)	2007	DBLP DOI BibTeX RDF	genetic algorithms, optimization, analog circuits
2	Yanghong Tan, Yigang He, Meirong Liu	Probabilistic Neural Network Based Method for Fault Diagnosis of Analog Circuits.	ISNN	2007	DBLP DOI BibTeX RDF
2	Almitra Pradhan, Ranga Vemuri	Regression based circuit matrix models for accurate performance estimation of analog circuits.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
2	Henry H. Y. Chan, Zeljko Zilic	A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Qingjian Ji, Youren Wang, Min Xie, Jiang Cui	Research on Fault-Tolerance of Analog Circuits Based on Evolvable Hardware.	ICES	2007	DBLP DOI BibTeX RDF	EHW, FPACA, Amplifier circuit, Fault-tolerance, Evolutionary algorithm
2	Dana Angluin, James Aspnes, Jiang Chen, Lev Reyzin	Learning Large-Alphabet and Analog Circuits with Value Injection Queries.	COLT	2007	DBLP DOI BibTeX RDF
2	Xin Li, Brian Taylor, YuTsun Chien, Lawrence T. Pileggi	Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Mingjing Chen, Alex Orailoglu	Circuit-level mismatch modelling and yield optimization for CMOS analog circuits.	ICCD	2007	DBLP DOI BibTeX RDF
2	Raffaella Gentilini, Klaus Schneider, Alexander Dreyer	Three-valued automated reasoning on analog properties.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	(multi valued) temporal logics & model checking, interval arithmetic, analog circuits
2	C.-J. Richard Shi, Michael W. Tian, Guoyong Shi	Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Haralampos-G. D. Stratigopoulos, Yiorgos Makris	Concurrent detection of erroneous responses in linear analog circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Fang Liu, Sule Ozev, Martin A. Brooke	Identifying the Source of BW Failures in High-Frequency Linear Analog Circuits Based on S-Parameter Measurements.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Mohammad Maymandi-Nejad, Manoj Sachdev	DTMOS Technique for Low-Voltage Analog Circuits.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Mohamed H. Zaki, Sofiène Tahar, Guy Bois	A practical approach for monitoring analog circuits.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF
2	Maria José P. Dantas, Leonardo da C. Brito, Paulo Henrique Portela de Carvalho	Multi-objective Memetic Algorithm Applied to the Automated Synthesis of Analog Circuits.	IBERAMIA-SBIA	2006	DBLP DOI BibTeX RDF	multi-objective memetic algorithm, 2D representation, analog circuit, building-blocks, automated synthesis
2	Xiaoying Wang, Lars Hedrich	An approach to topology synthesis of analog circuits using hierarchical blocks and symbolic analysis.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Ritochit Chakraborty, Mukesh Ranjan, Ranga Vemuri	Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction.	VLSI Design	2006	DBLP DOI BibTeX RDF
2	Trent McConaghy, Georges G. E. Gielen	Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns.	DATE	2006	DBLP DOI BibTeX RDF
2	Hui Zhang, Yang Zhao, Alex Doboli	ALAMO: an improved alpha-space based methodology for modeling process parameter variations in analog circuits.	DATE	2006	DBLP DOI BibTeX RDF
2	Abhishek Somani, P. P. Chakrabarti, Amit Patra	A model-based hybrid evolutionary algorithm for fast yield-inclusive design space exploration of analog circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Yukiya Miura, Jiro Kato	Fault Diagnosis of Analog Circuits Based on Adaptive Test and Output Characteristics.	DFT	2006	DBLP DOI BibTeX RDF
2	Ying Wei, Alex Doboli	Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling.	DAC	2006	DBLP DOI BibTeX RDF	nonlinear macromodel, structural macromodel, analog circuits
2	Yiu-Cheong Tam, Evangeline F. Y. Young, Chris C. N. Chu	Analog placement with symmetry and other placement constraints.	ICCAD	2006	DBLP DOI BibTeX RDF	symmetry constraints, placement, analog circuits, sequence-pair
2	Tathagato Rai Dastidar, P. P. Chakrabarti, Partha Ray	A synthesis system for analog circuits based on evolutionary search and topological reuse.	IEEE Trans. Evolutionary Computation	2005	DBLP DOI BibTeX RDF
2	Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi	Hierarchical approach to exact symbolic analysis of large analog circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy	Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	Defect Oriented Testing (DOT), dynamic supply current (IDD), wavelet transform, Fourier transform
2	Anuradha Agarwal, Glenn Wolfe, Ranga Vemuri	Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	performance modeling, circuit sizing, analog synthesis
2	Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu, Lei He	Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri, Georges G. E. Gielen	Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Sudarshan Bahukudumbi, Krishna Bharath	A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Tathagato Rai Dastidar, P. P. Chakrabarti	A Verification System for Transient Response of Analog Circuits Using Model Checking.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Fang Liu, Jacob J. Flomenberg, Devaka V. Yasaratne, Sule Ozev	Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing.	DATE	2005	DBLP DOI BibTeX RDF
2	Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen	CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming.	DATE	2005	DBLP DOI BibTeX RDF
2	Christian Falconi, Giuliano Guarino, Arnaldo D'Amico	Op amp tuning for high accuracy deep sub-micron CMOS analog circuits [voltage regulator example].	ISCAS	2005	DBLP DOI BibTeX RDF
2	Trent McConaghy, Georges G. E. Gielen	IBMG: interpretable behavioral model generator for nonlinear analog circuits via canonical form functions and genetic programming.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Peng Wang, Shiyuan Yang	Soft fault test and diagnosis for analog circuits.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Yukiya Miura	Characteristics of Fault Diagnosis for Analog Circuits Based on Preset Test.	DFT	2005	DBLP DOI BibTeX RDF
2	Hamid Reza Sadr M. N	A Novel Approach to the Design of a Linearized Widely Tunable Very Low Power and Low Noise Differential Transconductor.	PATMOS	2005	DBLP DOI BibTeX RDF	Differential transconductors, negative resistors, analog circuits and filters, widely tunable circuits, GHz range frequencies, continuous-time filters, Q-enhanced active filters, Gm-C filters, low power, RF, VCO, low noise
2	Göran Jerke, Jens Lienig	Hierarchical current-density verification in arbitrarily shaped metallization patterns of analog circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
2	Sule Ozev, Alex Orailoglu	Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
2	Chun-Lung Hsu	Control and Observation Structure for Analog Circuits with Current Test Data.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	current store cell (CSC), controllability, observability, analog circuit, current-mode
2	Stephen J. Spinks, Chris D. Chalk, Ian M. Bell, Mark Zwolinski	Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	analog test generation, fault modeling, fault simulation, catastrophic faults, supply current monitoring
2	Achintya Halder, Abhijit Chatterjee	Automated Test Generation and Test Point Selection for Specification Test of Analog Circuits.	ISQED	2004	DBLP DOI BibTeX RDF	test point selection, automated test generation, specification testing, parametric failure
2	Donghoon Han, Abhijit Chatterjee	Device Resizing Based Optimization of Analog Circuits for Reduced Test Cost: Cost Metric and Case Study.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
2	Ganesh Srinivasan, Shalabh Goyal, Abhijit Chatterjee	Reconfiguration for Enhanced ALternate Test (REALTest) of Analog Circuits.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
2	Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi	Hierarchical approach to exact symbolic analysis of large analog circuits.	DAC	2004	DBLP DOI BibTeX RDF	MEMS and/or RF design tools, behavioral modeling, analog, circuit simulation, symbolic analysis, mixed-signal
2	S. Nagar, Baquer Mazhari	A New Approach To Topology Selection For Cell-Level Analog Circuits.	VLSI Design	2004	DBLP DOI BibTeX RDF
2	Xiaoling Huang, H. Alan Mantooth	Identification and Modeling of Nonlinear Dynamic Behavior in Analog Circuits.	DATE	2004	DBLP DOI BibTeX RDF
2	Sheldon X.-D. Tan, Zhenyu Qi, Hang Li	Hierarchical Modeling and Simulation of Large Analog Circuits.	DATE	2004	DBLP DOI BibTeX RDF
2	Lutz Näthke, Volodymyr Burkhay, Lars Hedrich, Erich Barke	Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques.	DATE	2004	DBLP DOI BibTeX RDF
2	Yukiya Miura	Fault Diagnosis of Analog Circuits by Operation-Region Model and X-Y Zoning Method.	DFT	2004	DBLP DOI BibTeX RDF
2	Jorge Luís Machado do Amaral, José Franco Machado do Amaral, Ricardo Tanscheit, Marco Aurélio Cavalcanti Pacheco	An Immune Inspired Fault Diagnosis System for Analog Circuits using Wavelet Signatures.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
2	Pedro F. Vieira, Leonardo Bruno de Sá, João P. B. Botelho, Antonio Carneiro de Mesquita Filho	Evolutionary Synthesis of Analog Circuits Using Only MOS Transistors.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
2	Junwei Hou, Abhijit Chatterjee	Concurrent transient fault simulation for analog circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
2	Haralampos-G. D. Stratigopoulos, Yiorgos Makris	Concurrent Error Detection in Linear Analog Circuits Using State Estimation.	ITC	2003	DBLP DOI BibTeX RDF
2	Ramakrishna Voorakaranam, Randy Newby, Sasikumar Cherubal, Bob Cometta, Thomas Kuehl, David M. Majernik, Abhijit Chatterjee	Production Deployment of a Fast Transient Testing Methodology for Analog Circuits : Case Study and Results.	ITC	2003	DBLP DOI BibTeX RDF