Search results for "analog design"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Göran Jerke, Jens Lienig	Constraint-driven design: the next step towards analog design automation.	ISPD	2009	DBLP DOI BibTeX RDF	constraint-driven design, constraints, layout, physical design, analog design
2	Matthew Webb, Hua Tang	Analog design retargeting by design knowledge reuse and circuit synthesis.	ISCAS	2008	DBLP DOI BibTeX RDF
2	Saurabh Sinha, Asha Balijepalli, Yu Cao	A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design.	ISQED	2008	DBLP DOI BibTeX RDF	Schottky barrier, analog design metrics, modeling, CNT
2	Peter R. Kinget	Device Mismatch: An Analog Design Perspective.	ISCAS	2007	DBLP DOI BibTeX RDF
2	S. Lesueur, Daniel Massicotte, P. Sicard	A full-differential analog design of an indirect inverse control law based on neural networks.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Shekhar Y. Borkar, Robert W. Brodersen, Jue-Hsien Chern, Eric Naviasky, D. Saias, Charles Sodini	Tomorrow's analog: just dead or just different?	DAC	2006	DBLP DOI BibTeX RDF	analog CAD tools, analog design methodologies, mixed-signal design, analog design, RF design
2	Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eduardo Conrad Jr., Sergio Bampi	T-shaped association of transistors: modeling of multiple channel lengths and regular associations.	SBCCI	2005	DBLP DOI BibTeX RDF	associations of transistors, modeling, analog design, MOSFET
2	Fernando De Bernardinis, Alberto L. Sangiovanni-Vincentelli	A Methodology for System-Level Analog Design Space Exploration.	DATE	2004	DBLP DOI BibTeX RDF
2	Eric E. Fabris, Luigi Carro, Sergio Bampi	Modeling and designing high performance analog reconfigurable circuits.	SBCCI	2004	DBLP DOI BibTeX RDF	analog programmability, band-pass sigma-delta modulator, analog design, FPAA
2	Danica Stefanovic, Maher Kayal, Marc Pastre, Vanco B. Litovski	Procedural Analog Design (PAD) Tool.	ISQED	2003	DBLP DOI BibTeX RDF
2	Alfredo Arnaud, Carlos Galup-Montoro	Simple noise formulas for MOS analog design.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Hongzhou Liu, Amith Singhee, Rob A. Rutenbar, L. Richard Carley	Remembrance of circuits past: macromodeling by data mining in large analog design spaces.	DAC	2002	DBLP DOI BibTeX RDF
2	Pierluigi Daglio, M. Araldi, M. Morbarigazzi, Carlo Roma	A Fully Qualified Analog Design Flow for Non Volatile Memories Technologies.	ISQED	2001	DBLP DOI BibTeX RDF
2	J. Sevenhans, D. Haspeslagh, Jacques Wenin	Wireless telecom silicon integration: analog design for radio, baseband and speech spectrum.	Wireless Networks	1998	DBLP DOI BibTeX RDF
2	G. Droege, M. Thole, Ernst-Helmut Horneber	EASY - a System for Computer-Aided Examination of Analog Circuits.	DATE	1998	DBLP DOI BibTeX RDF	analog design system, computer-aided design, analog circuits, symbolic analysis, qualitative analysis
2	D. J. Klein, M. L. Manwaring	A Differential Model Approach To Analog Design Automation.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF
2	Wallace B. Leigh	A personal computer based VLSI design curriculum.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	VLSI design curriculum, teaching institutions, capstone VLSI course, analog design course, digital design synthesis course, teaching curriculum, VLSI, design methodology, integrated circuit design, circuit CAD, personal computers, computer aided instruction, microcomputer applications, electronic engineering education
1	Jan Craninckx	CMOS software-defined radio transceivers: Analog design in digital technology.	IEEE Communications Magazine	2012	DBLP DOI BibTeX RDF
1	Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos	Ordinary Kriging metamodel-assisted Ant Colony algorithm for fast analog design optimization.	ISQED	2012	DBLP DOI BibTeX RDF
1	Supriyo Maji, Pradip Mandal	Effcient approaches to overcome non-convexity issues in analog design automation.	ISQED	2012	DBLP DOI BibTeX RDF
1	Pierre Dautriche	Analog design trends and challenges in 28 and 20nm CMOS technology.	ESSCIRC	2011	DBLP DOI BibTeX RDF
1	Bradley N. Bond, Luca Daniel	Automated compact dynamical modeling: an enabling tool for analog designers.	DAC	2010	DBLP DOI BibTeX RDF	parameterized modeling, semidefinite programming, model reduction, analog design, compact modeling
1	Dalila Salhi, Balwant Godara	A 75dB-gain Low-power, Low-noise Amplifier for Low-frequency Bio-signal Recording.	DELTA	2010	DBLP DOI BibTeX RDF	bio-amplifier, bio-signals, low frequency, low-power, Analog design, biomedical application, OTA, low-noise
1	B. K. Mishra, Sandhya Save	Novel CAD Design Methodology for Two Stage Opamp with Noise-Power Balance.	ICSAP	2010	DBLP DOI BibTeX RDF	Analog circuit designs methodologies, Analog design automation, Op-amps, AMS, Simulated Annealing, CAD, SoC, ASIC, SPICE, EDA tools
1	Kenneth S. Kundert, Henry Chang	Model-based functional verification.	DAC	2010	DBLP DOI BibTeX RDF
1	Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang	Performance-driven analog placement considering boundary constraint.	DAC	2010	DBLP DOI BibTeX RDF	analog placement, boundary constraint, symmetry
1	Saurabh Sinha, Jounghyuk Suh, Bertan Bakkaloglu, Yu Cao	Workload-aware neuromorphic design of low-power supply voltage controller.	ISLPED	2010	DBLP DOI BibTeX RDF	neuromorphic engineering, DVS, spiking neurons
1	Vassilios Gerousis	Physical design implementation for 3D IC: methodology and tools.	ISPD	2010	DBLP DOI BibTeX RDF	3D IC stack, micro-bump, physical design tools, silicon interposer, methodology, tsv
1	Benoit Dubois, Jean-Baptiste Kammerer, Luc Hebrard, Francis Braun	Modelling of hot-carrier degradation and its application for analog design for reliability.	Microelectronics Journal	2009	DBLP DOI BibTeX RDF
1	Mohamed Dessouky	Analog design migration: An overview.	ICECS	2009	DBLP DOI BibTeX RDF
1	Xin Pan, Helmut Graeb	Degradation-aware analog design flow for lifetime yield analysis and optimization.	ICECS	2009	DBLP DOI BibTeX RDF
1	Purushothaman Srinivasan, Andrew Marshall	Correlating op-amp circuit noise with device flicker (1/f) noise for analog design applications.	SoCC	2009	DBLP DOI BibTeX RDF
1	Eric Soenen	Physical design methodology for analog circuitsin a system-on-a-chip environment.	ISPD	2009	DBLP DOI BibTeX RDF	analog design automation
1	Bo Liu, Francisco V. Fernández, Georges G. E. Gielen, R. Castro-López, Elisenda Roca	A memetic approach to the automatic design of high-performance analog integrated circuits.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Analog circuit sizing, analog design automation, constrained optimization, memetic algorithm
1	Noëlle Lewis, Michel Billaud, Didier Geoffroy, Philippe Cazenave, Thomas Zimmer	A Distance Measurement Platform Dedicated to Electrical Engineering.	TLT	2009	DBLP DOI BibTeX RDF	e-Learning tools, analog design and test, integrated circuits, remote laboratories, electrical engineering
1	Jaeha Kim	Mixed-Signal System Verification: A High-Speed Link Example.	CAV	2009	DBLP DOI BibTeX RDF	analog and mixed-signal verification, analog design intent, linear system models
1	Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho	Design methods for pipeline & delta-sigma A-to-D converters with convex optimization.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín	Techniques for the Design of Low Voltage Power Efficient Analog and Mixed Signal Circuits.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Mark R. Greenstreet	Verifying VLSI Circuits.	ATVA	2009	DBLP DOI BibTeX RDF
1	Gabriel Oltean, Sorin Hintea, Emilia Sipos	A Genetic Algorithm-Based Multiobjective Optimization for Analog Circuit Design.	KES	2009	DBLP DOI BibTeX RDF	Pareto ranking, genetic algorithm, multiobjective optimization, Pareto front, analog circuit design
1	Christopher M. Twigg, Paul E. Hasler	Incorporating Large-Scale FPAAs Into Analog Design and Test Courses.	IEEE Trans. Education	2008	DBLP DOI BibTeX RDF
1	Udo Sobe, Karl-Heinz Rooch, Andreas Ripp, Michael Pronath	Robust Analog Design for Automotive Applications by Design Centering with Safe Operating Areas.	ISQED	2008	DBLP DOI BibTeX RDF	Design Centering, Safe Operating Area, Self-Biasing Cascode, WiCKeD, Constraint Matrix, Reliability, Automotive, OTA
1	Fernando da Rocha Paixão Cortes, Sergio Bampi	A 40mhz 70db gain variable gain amplifier design using the gm/id design method.	SBCCI	2008	DBLP DOI BibTeX RDF	Variable Gain Amplifier (VGA), cmos analog design, rf front-end, amplifier
1	Peng Gao, Trent McConaghy, Georges G. E. Gielen	Importance sampled circuit learning ensembles for robust analog IC design.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Juraj Brenkus, Viera Stopjaková, Jozef Mihálov	Experimental Analog Circuit for Parametric Test Methods Efficiency Evaluation.	DDECS	2008	DBLP DOI BibTeX RDF
1	Thomas Jambor, Daniel Zaum, Markus Olbrich, Erich Barke	A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles.	DDECS	2008	DBLP DOI BibTeX RDF
1	Shubhankar Basu, Balaji Kommineni, Ranga Vemuri	Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Sani R. Nassif	Model to Hardware Matching for nm Scale Technologies.	PATMOS	2008	DBLP DOI BibTeX RDF
1	Lorenzo Petroli, Carlos Arthur Lang Lisbôa, Fernanda Lima Kastensmidt, Luigi Carro	Majority Logic Mapping for Soft Error Dependability.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Majority gates, Fault tolerance, SET, Majority logic
1	Benoit Dubois, Jean-Baptiste Kammerer, Luc Hebrard, Francis Braun	Analytical Modeling of Hot-Carrier Induced Degradation of MOS Transistor for Analog Design for Reliability.	ISQED	2007	DBLP DOI BibTeX RDF
1	David E. Duarte, Greg Taylor, Keng L. Wong, Usman Mughal, George Geannopoulos	Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor.	ISLPED	2007	DBLP DOI BibTeX RDF	sensor calibration error, temperature sensing, thermal management, analog design
1	Alfredo Arnaud, Martin Bremermann, Joel Gak, Matías R. Miguez	On the design of ultra low noise amplifiers for ENG recording.	SBCCI	2007	DBLP DOI BibTeX RDF	low power, CMOS, analog design, low noise
1	Burcu Erkmen, Tülay Yildirim	CSFNN Synapse and Neuron Design Using Current Mode Analog Circuitry.	KES	2007	DBLP DOI BibTeX RDF	Conic Section Function Neural Networks, Current Mode Analog Design, Neuron and Synapse Circuitry
1	Daniel Mueller, Helmut E. Graeb, Ulf Schlichtmann	Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming.	DATE	2007	DBLP DOI BibTeX RDF
1	Reimund Wittmann, Massimo Vanzi, Hans-Joachim Wassener, Navraj Nandra, Joachim Kunkel, Jose Franca, Christian Münker	Life begins at 65: unless you are mixed signal?	DATE	2007	DBLP DOI BibTeX RDF
1	Lorenzo Petroli, Carlos Arthur Lang Lisbôa, Fernanda Lima Kastensmidt, Luigi Carro	Using majority logic to cope with long duration transient faults.	SBCCI	2007	DBLP DOI BibTeX RDF	long duration transient faults, majority logic
1	Jian Wang, Xin Li, Lawrence T. Pileggi	Parameterized Macromodeling for Analog System-Level Design Exploration.	DAC	2007	DBLP DOI BibTeX RDF
1	Rene Penning de Vries	Systems, Nano-technology and SiP.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi	Robust Analog/RF Circuit Design With Projection-Based Performance Modeling.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Sherif Hammouda, Hazem Said, Mohamed Dessouky, Mohamed Tawfik, Quang Nguyen, Wael M. Badawy, Hazem M. Abbas, Hussein I. Shahein	Chameleon ART: a non-optimization based analog design migration framework.	DAC	2006	DBLP DOI BibTeX RDF	analog reuse, design extraction, layout compaction, layout retargeting, circuit sizing
1	Pablo Aguirre, Fernando Silveira	Bias circuit design for low-voltage cascode transistors.	SBCCI	2006	DBLP DOI BibTeX RDF	CMOS, low voltage, analog design
1	Alessandro Girardi, Sergio Bampi	Power constrained design optimization of analog circuits based on physical gm/ID characteristics.	SBCCI	2006	DBLP DOI BibTeX RDF	simulated annealing, synthesis, analog design
1	Hamilton Klimach, Márcio C. Schneider, Carlos Galup-Montoro	A test chip for automatic MOSFET mismatch characterization.	SBCCI	2006	DBLP DOI BibTeX RDF	matching, characterization, analog design, MOSFET, mismatch
1	Fernando De Bernardinis, Pierluigi Nuzzo, Alberto L. Sangiovanni-Vincentelli	Robust system level design with analog platforms.	ICCAD	2006	DBLP DOI BibTeX RDF	analog platforms, robust hierarchical design, system-level design
1	Á. Michels, Lorenzo Petroli, Carlos Arthur Lang Lisbôa, Fernanda Gusmão de Lima Kastensmidt, Luigi Carro	SET Fault Tolerant Combinational Circuits Based on Majority Logic.	DFT	2006	DBLP DOI BibTeX RDF
1	S. Alenin, D. Spady, V. Ivanov	A low ripple on-chip charge pump for bootstrapping of the noise-sensitive nodes.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Henning Gundersen, Yngvar Berg	A novel ternary more, less and equality circuit using recharged semi-floating gate devices.	ISCAS	2006	DBLP DOI BibTeX RDF
1	M. Jiménez, Antonio Torralba, Ramón González Carvajal, Jaime Ramírez-Angulo	A new low-voltage CMOS unity-gain buffer.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Henning Gundersen, Yngvar Berg	A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih Chen, Wanju Chiang	Performance-centering optimization for system-level analog design exploration.	ICCAD	2005	DBLP BibTeX RDF
1	Alfredo Arnaud	An efficient chopper amplifier, using a switched Gm-C Filter technique.	SBCCI	2005	DBLP DOI BibTeX RDF	low-power, CMOS, analog design
1	Alfredo Arnaud, Rafaella Fiorelli, Carlos Galup-Montoro	On the design of very small transconductance OTAs with reduced input offset.	SBCCI	2005	DBLP DOI BibTeX RDF	low-power, CMOS, analog design
1	Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang	Placement with symmetry constraints for analog layout design using TCG-S.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Georges G. E. Gielen, Trent McConaghy, Tom Eeckelaert	Performance space modeling for hierarchical synthesis of analog integrated circuits.	DAC	2005	DBLP DOI BibTeX RDF	hierarchical synthesis
1	Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen	CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming.	DATE	2005	DBLP DOI BibTeX RDF
1	Fernando De Bernardinis, Pierluigi Nuzzo, Pierangelo Terreni, Alberto L. Sangiovanni-Vincentelli	Enriching an analog platform for analog-to-digital converter design.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Fathi A. Farag, Carlos Galup-Montoro, Márcio C. Schneider	Inverter-based switched current circuit for very low-voltage and low-power applications.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Peter R. Wilson, Reuben Wilcock	Behavioural modeling and simulation of a switched-current phase locked loop.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Jihyun Lee, Yong-Bin Kim	ASLIC: A Low Power CMOS Analog Circuit Design Automation.	ISQED	2005	DBLP DOI BibTeX RDF
1	Carlo Roma, Pierluigi Daglio, Guido De Sandre, Marco Pasotti, Marco Poles	How Circuit Analysis and Yield Optimization Can Be Used To Detect Circuit Limitations Before Silicon Results.	ISQED	2005	DBLP DOI BibTeX RDF
1	Tathagato Rai Dastidar, P. P. Chakrabarti, Partha Ray	A synthesis system for analog circuits based on evolutionary search and topological reuse.	IEEE Trans. Evolutionary Computation	2005	DBLP DOI BibTeX RDF
1	Alessandro Savio, Luigi Colalongo, Zsolt Miklós Kovács-Vajna, Michele Quarantelli	Scaling rules and parameter tuning procedure for analog design reuse in technology migration.	ISCAS	2004	DBLP BibTeX RDF
1	Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Jesús Velarde-Ramírez	A precise CMOS mismatch model for analog design from weak to strong inversion.	ISCAS	2004	DBLP DOI BibTeX RDF
1	Alfredo Arnaud, Carlos Galup-Montoro	A fully integrated physical activity sensing circuit for implantable pacemakers.	SBCCI	2004	DBLP DOI BibTeX RDF	low-power, CMOS, analog design, biomedical
1	Hamilton Klimach, Alfredo Arnaud, Márcio C. Schneider, Carlos Galup-Montoro	Characterization of MOS transistor current mismatch.	SBCCI	2004	DBLP DOI BibTeX RDF	matching, analog design, MOSFET, mismatch, compact models
1	Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri	Fast and accurate parasitic capacitance models for layout-aware.	DAC	2004	DBLP DOI BibTeX RDF	layout aware, parasitic estimation, analog synthesis
1	Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi	Robust analog/RF circuit design with projection-based posynomial modeling.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Hassan Aboushady, L. de Lamarre, Nicolas Beilleau, Marie-Minerve Louërat	Automatic Synthesis and Simulation of Continuous-Time [Sigma-Delta] Modulators.	DATE	2004	DBLP DOI BibTeX RDF
1	João Ramos, Kenneth Francken, Georges G. E. Gielen, Michiel Steyaert	Knowledge- and optimization-based design of RF power amplifiers.	ISCAS	2004	DBLP DOI BibTeX RDF
1	Vojkan Vidojkovic, Johan van der Tang, Eric Hanssen, Arjan J. Leeuwenburgh, Arthur H. M. van Roermund	Low voltage, low power folded-switching mixer with current-reuse in 0.18µm CMOS.	ISCAS	2004	DBLP DOI BibTeX RDF
1	Bo-Sung Kim, Young-Gi Kim, Soon-Yang Hong	Low Power 260 k Color TFT LCD One-Chip Driver IC.	ISQED	2004	DBLP DOI BibTeX RDF
1	Amit Gupta, Steven P. Levitan, Leo Selavo, Donald M. Chiarulli	High-Speed Optoelectronics Receivers in SiGe.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Jean Michel Daga, Caroline Papaix, Marylene Combe, Emmanuel Racape, Vincent Sialelli	Embedded EEPROM Speed Optimization Using System Power Supply Resources.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Mile K. Stojcev	Analog Design for CMOS VLSI Systems: Franco Maloberti (Ed.); Kluwer Academic Publishers, Dordrecht, 2001, 374 pages, plus XIII, hardcover, ISBN 0-7923-7550-5.	Microelectronics Journal	2003	DBLP DOI BibTeX RDF
1	Patricia Giacomelli, Márcio C. Schneider, Carlos Galup-Montoro	MOSVIEW: A Graphical Tool for MOS Analog Design.	MSE	2003	DBLP DOI BibTeX RDF
1	Maria del Mar Hershenson	Efficient description of the design space of analog circuits.	DAC	2003	DBLP DOI BibTeX RDF	optimization, verification, synthesis, analog, circuits, convex programming, geometric program
1	Puneet Gupta, Andrew B. Kahng	Manufacturing-Aware Physical Design.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Dean Liu, Stefanos Sidiropoulos, Mark Horowitz	A Framework for Designing Reusable Analog Circuits.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Esteban Tlelo-Cuautle, Alejandro Díaz-Sánchez	An heuristic circuit-generation technique for the design-automation of analog circuits.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Eric E. Fabris, Luigi Carro, Sergio Bampi	A Universal High-Performance Analog Interface for Signal Processing SOCs.	SBCCI	2003	DBLP DOI BibTeX RDF