Search results for "analog integrated circuits"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Wimol San-Um, Masayoshi Tachibana	Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits.	SBCCI	2009	DBLP DOI BibTeX RDF	impulse stimulation, linear analog integrated circuits, response sampling technique, built-in self test
3	Wim Verhaegen, Geert Van der Plas, Georges G. E. Gielen	Automated test pattern generation for analog integrated circuits.	VTS	1997	DBLP DOI BibTeX RDF	automated test pattern generation, generated fault list, optimal test signals, statistical fluctuations, statistical test criterion, ATPG algorithm, analogue integrated circuits, analog integrated circuits
2	Michael Eick, Martin Strasser, Helmut E. Graeb, Ulf Schlichtmann	Automatic generation of hierarchical placement rules for analog integrated circuits.	ISPD	2010	DBLP DOI BibTeX RDF	hierarchical placement rules, constraints, placement, analog integrated circuits
2	Bo Liu, Francisco V. Fernández, Georges G. E. Gielen, R. Castro-López, Elisenda Roca	A memetic approach to the automatic design of high-performance analog integrated circuits.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Analog circuit sizing, analog design automation, constrained optimization, memetic algorithm
2	Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu	Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Viera Stopjaková, P. Malosek, D. Micusík, M. Matej, Martin Margala	Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	artificial neural networks, analog test, catastrophic faults, supply current monitoring
2	Sina Balkir, Günhan Dündar, Guner Alpaydin	Evolution Based Synthesis of Analog Integrated Circuits and Systems.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
2	Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen	Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
2	Ken Yamamoto, Minoru Fujishima, Koichiro Hoh	Optimization of shield structures in analog integrated circuits.	ISCAS	2003	DBLP DOI BibTeX RDF
2	D. Micusík, Viera Stopjaková, Lubica Benusková	Application of Feed-forward Artificial Neural Networks to the Identification of Defective Analog Integrated Circuits.	Neural Computing and Applications	2002	DBLP DOI BibTeX RDF	Circuits response investigation, Fault modelling and simulation, Resilient-backpropagation neural networks, Signal filtering, Supply current analysis
2	Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen	An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits.	DAC	2002	DBLP DOI BibTeX RDF	performance modeling for analog circuits, posynomial response surface modeling, geometric programming
2	Diego Vázquez, Gloria Huertas, Gildas Leger, Adoración Rueda, José L. Huertas	Practical solutions for the application of the oscillation-based-test in analog integrated circuits.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Geert Van der Plas, Geert Debyser, Francky Leyn, Koen Lampaert, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen, Petar Veselinovic, Domine Leenaerts	AMGIE-A synthesis environment for CMOS analog integrated circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
2	Sheldon X.-D. Tan, C.-J. Richard Shi	Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
2	Tao Pi, C.-J. Richard Shi	Multi-terminal determinant decision diagrams: a new approach to semi-symbolic analysis of analog integrated circuits.	DAC	2000	DBLP DOI BibTeX RDF
2	Zhihua Wang, Georges G. E. Gielen, Willy M. C. Sansen	Probabilistic fault detection and the selection of measurements for analog integrated circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
2	Diego Vázquez, José L. Huertas, Adoración Rueda	Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design.	VTS	1996	DBLP DOI BibTeX RDF	sw-op amp design, CMOS implementations, design efforts, cell design, integrated circuit testing, design for testability, DFT, integrated circuit design, power dissipation, operational amplifiers, area, analogue integrated circuits, IC testing, analog integrated circuits, CMOS analogue integrated circuits
2	Qicheng Yu, Carl Sechen	Approximate symbolic analysis of large analog integrated circuits.	ICCAD	1994	DBLP DOI BibTeX RDF
2	Georges G. E. Gielen, Zhihua Wang, Willy M. C. Sansen	Fault detection and input stimulus determination for the testing of analog integrated circuits based on power-supply current monitoring.	ICCAD	1994	DBLP DOI BibTeX RDF
1	Laure Buhry, Michele Pace, Sylvain Saïghi	Global parameter estimation of an Hodgkin-Huxley formalism using membrane voltage recordings: Application to neuro-mimetic analog integrated circuits.	Neurocomputing	2012	DBLP DOI BibTeX RDF
1	Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin, Soon-Jyh Chang	Routability-driven placement algorithm for analog integrated circuits.	ISPD	2012	DBLP DOI BibTeX RDF
1	Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey	Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Michael Eick, Martin Strasser, Kun Lu, Ulf Schlichtmann, Helmut E. Graeb	Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Laure Buhry, Filippo Grassia, Audrey Giremus, Eric Grivel, Sylvie Renaud, Sylvain Saïghi	Automated Parameter Estimation of the Hodgkin-Huxley Model Using the Differential Evolution Algorithm: Application to Neuromimetic Analog Integrated Circuits.	Neural Computation	2011	DBLP DOI BibTeX RDF
1	Lihong Zhang, Zheng Liu	Directly performance-constrained template-based layout retargeting and optimization for analog integrated circuits.	Integration	2011	DBLP DOI BibTeX RDF
1	Parijat Mukherjee, G. Peter Fang, Rod Burt, Peng Li	Automatic stability checking for large linear analog integrated circuits.	DAC	2011	DBLP DOI BibTeX RDF
1	Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang	Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits.	DAC	2011	DBLP DOI BibTeX RDF
1	Hui Xu, Guoyong Shi, Xiaopeng Li	Hierarchical exact symbolic analysis of large analog integrated circuits by symbolic stamps.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Chien-Chih Huang, Jwu-E Chen, Pei-Wen Luo, Chin-Long Wey	Yield-award placement optimization for Switched-Capacitor analog integrated circuits.	SoCC	2011	DBLP DOI BibTeX RDF
1	J.-E. Chen, P.-W. Luo, C.-L. Wey	Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Zheng Liu, Lihong Zhang	A performance-constrained template-based layout retargeting algorithm for analog integrated circuits.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Ali Jafari, Saeed Sadri, Maryam Zekri	Design optimization of analog integrated circuits by using artificial neural networks.	SoCPaR	2010	DBLP DOI BibTeX RDF
1	Georges G. E. Gielen, Elie Maricau, Peter H. N. De Wit	Design automation towards reliable analog integrated circuits.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Mar Hershenson	Design platform for electrical and physical co-design of analog circuits.	ISPD	2010	DBLP DOI BibTeX RDF	design, analog, co-design
1	Trent McConaghy, Georges G. E. Gielen	Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Pieter Palmers, Trent McConaghy, Michiel Steyaert, Georges G. E. Gielen	Massively multi-topology sizing of analog integrated circuits.	DATE	2009	DBLP BibTeX RDF
1	Hussain Alzaher, Noman Tasadduq	A CMOS low power current-mode polyphase filter.	ISLPED	2009	DBLP DOI BibTeX RDF	CMOS analog integrated circuits, low power current mode circuit, polyphase filter
1	Rui He, Lihong Zhang	Artificial neural network application in analog layout placement design.	CCECE	2009	DBLP DOI BibTeX RDF
1	Adel Daouzli, Sylvain Saïghi, Michelle Rudolph, Alain Destexhe, Sylvie Renaud	Convergence in an Adaptive Neural Network: The Influence of Noise Inputs Correlation.	IWANN	2009	DBLP DOI BibTeX RDF	Neuromorphic Engineering, Silicon Neurons, Hodgkin-Huxley Model, STDP
1	Reza Hashemian	Use of local biasing in designing analog integrated circuits.	EIT	2008	DBLP DOI BibTeX RDF
1	Guo Yu, Peng Li	Yield-aware hierarchical optimization of large analog integrated circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Laurent Gatet, Hélène Tap-Béteille, Daniel Roviras, Francis Gizard	Integrated CMOS Analog Neural Network Ability to Linearize the Distorted Characteristic of HPA Embedded in Satellites.	DELTA	2008	DBLP DOI BibTeX RDF	CMOS Analog Integrated Circuits, Nonlinear Distortion, Predistorsion, Multi-Layer Perceptrons, Neural Network Architecture
1	Andrea Pugliese 0002, Francesco A. Amoroso, Gregorio Cappuccino, Giuseppe Cocorullo	Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers.	PATMOS	2008	DBLP DOI BibTeX RDF	CMOS analog integrated circuits, frequency compensation, operational amplifiers, transient response
1	Eduardo Conrad Jr., Fernando da Rocha Paixão Cortes, Sergio Bampi, Alessandro Girardi	Early voltage and saturation voltage improvement in deep sub-micron technologies using associations of transistors.	SBCCI	2008	DBLP DOI BibTeX RDF	TAT, TST, association of transistors, measurements, device modeling
1	Li Wang, Robert W. Newcomb	An adjustable CMOS floating resistor.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Lihong Zhang, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi	Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Matthew A. Smith, Lars A. Schreiner, Erich Barke, Volker Meyer zu Bexten	Algorithms for automatic length compensation of busses in analog integrated circuits.	ISPD	2007	DBLP DOI BibTeX RDF	analog routing, length compensation, net bundles, paired nets, virtual terminals, routing, EDA, RF, bus routing, IC-layout
1	Zhenhua Wang	Adaptive analog biasing: a robustness-enhanced low-power technique for analog baseband design.	ISLPED	2007	DBLP DOI BibTeX RDF	robustness enhancement, sensitivity reduction, low-power, low-energy, analog integrated circuits, biasing
1	César Augusto Prior, Cesar Ramos Rodrigues, João Baptista dos Santos Martins, André Luiz Aita, Filipe Costa Beber Vieira	Design of an integrated low power high CMRR instrumentation amplifier for biomedical applications.	SBCCI	2007	DBLP DOI BibTeX RDF	higth CMRR, low power, analog integrated circuits, current mode, instrumentation amplifier
1	Filipe Costa Beber Vieira, César Augusto Prior, Cesar Ramos Rodrigues, Leonardo Perin, João Baptista dos Santos Martins	Current mode instrumentation amplifier with rail-to-rail input and output.	SBCCI	2007	DBLP DOI BibTeX RDF	current mode instrumentation amplifier, rail-to-rail input and output, analog integrated circuits
1	Peter R. Kinget	Device Mismatch: An Analog Design Perspective.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Guido Stehr, Helmut E. Graeb, Kurt Antreich	Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Saied Hemati, Amir H. Banihashemi	Convergence Speed and Throughput of Analog Decoders.	IEEE Transactions on Communications	2007	DBLP DOI BibTeX RDF
1	Shouri Chatterjee, Yannis P. Tsividis, Peter R. Kinget	Ultra-Low Voltage Analog Integrated Circuits.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Andrzej Szymanski, Ewa Kurjata-Pfitzner	Effects of package and process variation on 2.4GHz analog integrated circuits.	Microelectronics Reliability	2006	DBLP DOI BibTeX RDF
1	Amir Zjajo, José Pineda de Gyvez, Guido Gronthoud	Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	structural fault modeling, analog fault modeling, Neyman-Pearson decision, fault detection, analog test, supply current monitoring
1	Fabio Lacerda, Stefano Pietri, Alfredo Olmos	A differential switched-capacitor amplifier with programmable gain and output offset voltage.	SBCCI	2006	DBLP DOI BibTeX RDF	differential to single ended, switched capacitor stage, analog integrated circuits
1	Antonio Petraglia, Jorge M. Cañive, Mariane R. Petraglia	Efficient Parametric Fault Detection in Switched-Capacitor Filters.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	allpass circuits, testing, fault diagnosis, filters, fault location, analog integrated circuits, switched-capacitor filters, circuit testing
1	Murari Kejariwal, Prasad Ammisetti, John Melanson	Built-in self-test mode in a multi-path feedforward compensated operational amplifier.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Lihong Zhang, Ulrich Kleine, Yingtao Jiang	An automated design tool for analog layouts.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Georges G. E. Gielen, Trent McConaghy, Tom Eeckelaert	Performance space modeling for hierarchical synthesis of analog integrated circuits.	DAC	2005	DBLP DOI BibTeX RDF	hierarchical synthesis
1	Daniel Mueller, Guido Stehr, Helmut E. Graeb, Ulf Schlichtmann	Deterministic approaches to analog performance space exploration (PSE).	DAC	2005	DBLP DOI BibTeX RDF	performance space exploration, pareto optimization, analog integrated circuits, fourier motzkin elimination
1	Saurabh Kumar Singh, T. K. Bhattacharyya, Ashudeb Dutta	Fully Integrated CMOS Frequency Synthesizer for ZigBee Applications.	VLSI Design	2005	DBLP DOI BibTeX RDF	CMOS RF, ZigBee, Phase locked loop, Analog integrated circuits, Frequency synthesizer
1	Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi	Template-driven parasitic-aware optimization of analog integrated circuit layouts.	DAC	2005	DBLP DOI BibTeX RDF	analog layout automation, optimization, sensitivity, parasitics
1	Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eduardo Conrad Jr., Sergio Bampi	T-shaped association of transistors: modeling of multiple channel lengths and regular associations.	SBCCI	2005	DBLP DOI BibTeX RDF	associations of transistors, modeling, analog design, MOSFET
1	Edward Ramsden, Garrison W. Greenwood, David Hunter	EARP-1 - An Evolvable Analog Research Platform.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
1	Roy Hartono, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi	Automatic Device Layout Generation for Analog Layout Retargeting.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Boris Murmann, Bernhard E. Boser	Digitally Assisted Analog Integrated Circuits.	ACM Queue	2004	DBLP DOI BibTeX RDF
1	Kamala Hariharan, Shoba Krishnan, V. P. Gopinath	Impact of Gate Leakage on the Performance of Analog Integrated Circuits - A Simulation Study.	ESA/VLSI	2004	DBLP BibTeX RDF
1	Tholom Kiely, Georges G. E. Gielen	Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines.	DATE	2004	DBLP DOI BibTeX RDF
1	Carlos Sánchez-López, Esteban Tlelo-Cuautle	Symbolic noise analysis in analog integrated circuits.	ISCAS	2004	DBLP BibTeX RDF
1	Shanthi Pavan	A fixed transconductance bias technique for CMOS analog integrated circuits.	ISCAS	2004	DBLP DOI BibTeX RDF
1	Jorge Aguila-Meza, Leticia Torres-Papaqui, Esteban Tlelo-Cuautle	Improving symbolic analysis in CMOS analog integrated circuits.	ISCAS	2004	DBLP BibTeX RDF
1	Antonio Petraglia, Jorge M. Cañive, Mariane R. Petraglia	A 0.8 mum CMOS switched-capacitor video filter.	SBCCI	2004	DBLP DOI BibTeX RDF	allpass circuits, testing, filters, analog integrated circuits, switched-capacitor filters
1	Guner Alpaydin, Sina Balkir, Günhan Dündar	An evolutionary approach to automatic synthesis of high-performance analog integrated circuits.	IEEE Trans. Evolutionary Computation	2003	DBLP DOI BibTeX RDF
1	Sheldon X.-D. Tan, C.-J. Richard Shi	Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis.	Integration	2003	DBLP DOI BibTeX RDF
1	Naresh Sarwabhotla, Arthi Kothandaraman	A Power-Efficient Level Converter Design For Multi-Supply Voltage CMOS Analog Integrated Circuits.	VLSI	2003	DBLP BibTeX RDF
1	Guido Stehr, Michael Pronath, Frank Schenkel, Helmut E. Graeb, Kurt Antreich	Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Tom Eeckelaert, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen	Generalized Posynomial Performance Modeling.	DATE	2003	DBLP DOI BibTeX RDF
1	Marco S. Dragic, Martin Margala	Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits.	DFT	2003	DBLP DOI BibTeX RDF
1	James Masciotti, Lessing Luu, Dariusz Czarkowski	CMOS current-mode analog circuit building blocks for rf DC-DC converter controllers.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Michael Pronath, Helmut E. Graeb, Kurt Antreich	A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits.	DATE	2002	DBLP DOI BibTeX RDF
1	Robert Schwencker, Frank Schenkel, Michael Pronath, Helmut E. Graeb	Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets.	DATE	2002	DBLP DOI BibTeX RDF
1	Viera Stopjaková, D. Micusík, Lubica Benusková, Martin Margala	Neural Networks-Based Parametric Testing of Analog IC. (PDF / PS)	DFT	2002	DBLP DOI BibTeX RDF
1	Lihong Zhang, Ulrich Kleine	A genetic approach to analog module placement with simulated annealing.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Edward Ramsden	The Isppac Family Of Reconfigurable Analog Circuits.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
1	Abdelhakim Khouas, Anne Derieux	FDP: fault detection probability function for analog circuits.	ISCAS	2001	DBLP DOI BibTeX RDF
1	C.-J. Richard Shi, Sheldon X.-D. Tan	Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Wanli Jiang, Bapiraju Vinnakota	Defect-oriented test scheduling.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Oscar Guerra, Elisenda Roca, Francisco V. Fernández, Ángel Rodríguez-Vázquez	A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits.	DATE	2000	DBLP DOI BibTeX RDF
1	Carlo Guardiani, Sharad Saxena, Patrick McNamara, Phillip Schumaker, Dale Coder	An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
1	Zheng Rong Yang, Mark Zwolinski, Chris D. Chalk, Alan Christopher Williams	Applying a robust heteroscedastic probabilistic neural network toanalog fault detection and classification.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	T. Asai, M. Ohtani, H. Yonezu	Analog integrated circuits for the Lotka-Volterra competitive neural networks.	IEEE Transactions on Neural Networks	1999	DBLP DOI BibTeX RDF
1	Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen	Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits.	DAC	1999	DBLP DOI BibTeX RDF
1	Huazhong Yang, Rong Luo, Hui Wang 0004, Runsheng Liu	An SA-Based Nonlinear Function Synthesizer for Linear Analog Integrated Circuits.	ASP-DAC	1999	DBLP DOI BibTeX RDF
1	Robert Schwencker, Josef Eckmueller, Helmut E. Graeb, Kurt Antreich	Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints.	DATE	1999	DBLP DOI BibTeX RDF
1	Tuna B. Tarim, Mohammed Ismail	Functional yield enhancement and statistical design of a low power transconductor.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Giri Devarayanadurg, Mani Soma, Prashant Goteti, Sam D. Huynh	Test set selection for structural faults in analog IC's.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	C. F. Prince, Vinita Vasudevan	Symbolic Analysis of Analog Integrated Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF
1	Andrea Boni, Andrea Pierazzi	Yield Enhancement by Multi-level Linear Modeling of Non-Idealities in an Interpolated Flash ADCs. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF	BiCMOS analog integrated circuits, Monte Carlo methods, Yield optimization, Analog-digital conversion