Search results for "application specific integrated circuits"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Nelson L. Passos, Edwin Hsing-Mean Sha, Liang-Fang Chao	Multi-dimensional interleaving for time-and-memory design optimization. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	multidimensional interleaving, time-and-memory design optimization, recursive time-critical sections, multi-dimensional problems, image processing, image processing, optimisation, application specific integrated circuits, application specific integrated circuits, circuit CAD, digital filters, digital filters, optimization technique, iteration space
2	Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy	Synthesis of application-specific highly efficient multi-mode cores for embedded systems.	ACM Trans. Embedded Comput. Syst.	2005	DBLP DOI BibTeX RDF	embedded systems, high level synthesis, synthesis, Digital signal processing (DSP), application specific integrated circuits (ASIC), reconfigurable system
2	Kurt Keutzer, Sharad Malik, A. Richard Newton	From ASIC to ASIP: The Next Design Discontinuity.	ICCD	2002	DBLP DOI BibTeX RDF	Programmable platforms, Design methodology, Application Specific Integrated Circuits, ASIC, Application Specific Instruction Set Processors, ASIP
1		Application-Specific Integrated Circuits.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
1	Arvind	Is hardware innovation over?	PPOPP	2010	DBLP DOI BibTeX RDF	hardware innovation, system-on-chip
1	Danilo Garbi Zutin, Michael E. Auer, A. Y. Al-Zoubi	Design and Verification of Application Specific Integrated Circuits in a Network of Online Labs.	iJOE	2009	DBLP DOI BibTeX RDF
1	Danilo Garbi Zutin, Michael E. Auer	Design and Test of Application-Specific Integrated Circuits by use of Mobile Clients.	iJOE	2009	DBLP DOI BibTeX RDF
1	Michael E. Auer, Danilo Garbi Zutin	Mobile Lab Clients for testing Application Specific Integrated Circuits in Education.	JDIM	2009	DBLP BibTeX RDF
1	P. Subramanian, Jagonda Patil, Manish Kumar Saxena	FPGA prototyping of a multi-million gate System-on-Chip (SoC) design for wireless USB applications.	IWCMC	2009	DBLP DOI BibTeX RDF	ECMA-368, FPGA-physical implementation, FPGA-synthesis, SoC (system-on-chip), synthesis constraints, FPGA, ASIC (application specific integrated circuits), functional verification, clock gating
1	Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang	A comparison of via-programmable gate array logic cell circuits.	FPGA	2009	DBLP DOI BibTeX RDF	logic cell, via-programmable gate arrays
1	Laurent Sauvage, Sylvain Guilley, Yves Mathieu	Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module.	TRETS	2009	DBLP DOI BibTeX RDF	EMA, security, FPGA, DPA, SCA, cartography
1	Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Scott A. Mahlke	Bridging the computation gap between programmable processors and hardwired accelerators.	HPCA	2009	DBLP DOI BibTeX RDF
1	Hugo Hedberg, Petr Dokládal, Viktor Öwall	Binary Morphology With Spatially Variant Structuring Elements: Algorithm and Architecture.	IEEE Transactions on Image Processing	2009	DBLP DOI BibTeX RDF
1	Yuzhong Jiao, Xin'an Wang, Xuewen Ni	A Fully Data-Driven Reconfigurable Architecture with Very Coarse-Grained Execution Units.	Infoscale	2009	DBLP DOI BibTeX RDF	Processing element (PE), Execution unit (EU), Very-coarse-grained, Fully-data-driven, Reconfigurable architecture
1	Danilo Garbi Zutin, Michael E. Auer	Design and test of Application-Specific Integrated Circuits by use of mobile clients.	ICDIM	2008	DBLP DOI BibTeX RDF
1	David Sheldon, Frank Vahid	Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	BRAM, high-throughput design, pattern counting, redesigning circuit, FPGA, design patterns, stream, memory, ASIC
1	Min Li, Bruno Bougard, David Novo, Liesbet Van der Perre, Francky Catthoor	How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach.	DAC	2008	DBLP DOI BibTeX RDF	baseband, low power, wireless, SDR
1	David Dickin, Lesley Shannon	Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms.	ASAP	2008	DBLP DOI BibTeX RDF
1	Philip Heng Wai Leong	Recent Trends in FPGA Architectures and Applications.	DELTA	2008	DBLP DOI BibTeX RDF	FPGA, applications
1	Theepan Moorthy, Andy Ye	A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays.	FPL	2008	DBLP DOI BibTeX RDF
1	Mark Hammerquist, Roman L. Lysecky	Design space exploration for application specific FPGAS in system-on-a-chip designs.	SoCC	2008	DBLP DOI BibTeX RDF
1	J. C. Chen, Shao-Yi Chien	CRISP: Coarse-Grained Reconfigurable Image Stream Processor for Digital Still Cameras and Camcorders.	IEEE Trans. Circuits Syst. Video Techn.	2008	DBLP DOI BibTeX RDF
1	Banit Agrawal, Timothy Sherwood	Ternary CAM Power and Delay Model: Extensions and Uses.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Didier Keymeulen, Adrian Stoica, Ricardo Salem Zebulum, Srinivas Katkoori, Pradeep Fernando, Hariharan Sankaran, Mohammad M. Mojarradi, Taher Daud	Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core.	ICES	2008	DBLP DOI BibTeX RDF	Self-Healing and Compensation, Self-reconfigurable, Field Programmable Analog Array
1	Domingos S. S. Carneiro, Paulo V. A. Pinheiro, Pedro H. Prudêncio, Daniel N. S. Cavalcante, Diego V. S. Sousa, Rudy M. Braquehais, Thially V. P. Marrocos, Marcial P. Fernandez	IP-checksum incremental update method proposal for efficient use of energy in wireless environments.	EATIS	2007	DBLP DOI BibTeX RDF	FPGA, mesh networks, checksum
1	Praveen R. Samala, Hamid Vakilzadian, Dietmar P. F. Möller	Modeling and simulation of common primitive operations used in block ciphers.	SCSC	2007	DBLP DOI BibTeX RDF	discrete event simulation, hardware modeling, encryption algorithms
1	Ricardo Salem Zebulum, Mohammad M. Mojarradi, Adrian Stoica, Didier Keymeulen, Taher Daud	Self-Reconfigurable Analog Arrays: Off-The Shelf Adaptive Electronics for Space Applications.	AHS	2007	DBLP DOI BibTeX RDF
1	Ian Kuon, Jonathan Rose	Measuring the Gap Between FPGAs and ASICs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Jiong Luo, Niraj K. Jha	Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Mehdi Baradaran Tahoori, Subhasish Mitra	Application-Dependent Delay Testing of FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Peter Tummeltshammer, James C. Hoe, Markus Püschel	Time-Multiplexed Multiple-Constant Multiplication.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Fan-Min Li, An-Yeu Wu	On the New Stopping Criteria of Iterative Turbo Decoding by Using Decoding Threshold.	IEEE Transactions on Signal Processing	2007	DBLP DOI BibTeX RDF
1	Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, Paul Chow	Routability of Network Topologies in FPGAs.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Adrian Stoica, Didier Keymeulen, Ricardo Salem Zebulum, Mohammad M. Mojarradi, Srinivas Katkoori, Taher Daud	Adaptive and Evolvable Analog Electronics for Space Applications.	ICES	2007	DBLP DOI BibTeX RDF	Adaptive Hardware, Field Programmable Arrays
1	Michael F. P. O'Boyle, François Bodin, Marcelo Cintra	Introduction to Part 2.	T. HiPEAC	2007	DBLP DOI BibTeX RDF
1	Arran Derbyshire, Tobias Becker, Wayne Luk	Incremental elaboration for run-time reconfigurable hardware designs.	CASES	2006	DBLP DOI BibTeX RDF	incremental elaboration, run-time reconfiguration, hardware compilation
1	Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, Li Jing	High-level synthesis challenges and solutions for a dynamically reconfigurable processor.	ICCAD	2006	DBLP DOI BibTeX RDF	high-level synthesis, dynamic reconfiguration, reconfigurable processor
1	Gabriella Kókai, Tonia Christ, Hans Holm Frühauf	Using Hardware-Based Particle Swarm Method for Dynamic Optimization of Adaptive Array Antennas.	AHS	2006	DBLP DOI BibTeX RDF
1	M. Watanabe, F. Kobayashi	Optically Reconfigurable Gate Arrays vs. ASICs.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Declan Hegarty, Steve McDonald	An FPGA-based Configurable Network Interface System.	ICN/ICONS/MCL	2006	DBLP DOI BibTeX RDF
1	Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J. M. Smit	An optimal architecture for a DDC.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Maya Gokhale	RAW keynote 1: the outer limits: reconfigurable computing in space and in orbit.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Paul Royal, Mitch Halpin, Ada Gavrilovska, Karsten Schwan	Utilizing Network Processors in Distributed Enterprise Environments.	NCA	2006	DBLP DOI BibTeX RDF
1	Lei Cheng, Martin D. F. Wong	Floorplan Design for Multimillion Gate FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Use of Computation-Unit Integrated Memories in High-Level Synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Bin Wu, Jianwen Zhu, Farid N. Najm	Dynamic-range estimation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	David G. Chinnery, Kurt Keutzer	Closing the power gap between ASIC and custom: an ASIC perspective.	DAC	2005	DBLP DOI BibTeX RDF	power, energy, custom, ASIC, comparison, standard cell
1	Ingrid Verbauwhede, Patrick Schaumont	Skiing the embedded systems mountain.	ACM Trans. Embedded Comput. Syst.	2005	DBLP DOI BibTeX RDF	Education, design space exploration, cosimulation
1	David E. Taylor, Andreas Herkersdorf, Andreas C. Döring, Gero Dittmann	Robust header compression (ROHC) in next-generation network processors.	IEEE/ACM Trans. Netw.	2005	DBLP DOI BibTeX RDF	ROHC, hardware assist, FPGA, ASIC, network processor, ASIP, reconfigurable hardware, header compression
1	Gerald R. Morris, Viktor K. Prasanna	An FPGA-Based Floating-Point Jacobi Iterative Solver.	ISPAN	2005	DBLP DOI BibTeX RDF
1	Haoxing Ren, David Zhigang Pan, David S. Kung	Sensitivity guided net weighting for placement-driven synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Byeong Kil Lee, Lizy Kurian John	Implications of Executing Compression and Encryption Applications on General Purpose Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Media compression, memory behavior, MediaZip benchmark, overhead memory bandwidth, encryption, encoding, decoding, workload characterization, decryption
1	Harm Peters, Ramanathan Sethuraman, Aleksandar Beric, P. Meuwissen, Srinivasan Balakrishnan, Carlos A. Alba Pinto, W. M. Kruijtzer, F. Ernst, Ghiath Alkadi, Jef L. van Meerbergen, Gerard de Haan	Application Specific Instruction-Set Processor Template for Motion Estimation in Video Applications.	IEEE Trans. Circuits Syst. Video Techn.	2005	DBLP DOI BibTeX RDF
1	Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha	Memory binding for performance optimization of control-flow intensive behavioral descriptions.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Dongming Peng, Mi Lu	Non-RAM-based architectural designs of wavelet-based digital systems based on novel nonlinear I/O data space transformations.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	High-level synthesis using computation-unit integrated memories.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Wei Qin, Subramanian Rajagopalan, Sharad Malik	A formal concurrency model based architecture description language for synthesis of software development tools.	LCTES	2004	DBLP DOI BibTeX RDF
1	Jie Guo, Michael Hosemann, Gerhard Fettweis	Employing Compilers for Determining Architectural Features of Application-Specific DSPs.	PARELEC	2004	DBLP DOI BibTeX RDF
1	Aleksandar Beric, Ramanathan Sethuraman, Harm Peters, Jef L. van Meerbergen, Gerard de Haan, Carlos A. Alba Pinto	A 27 mW 1.1 mm2 Motion Estimator for Picture-Rate Up-converter.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Ulrich Brenner, Jens Vygen	Legalizing a placement with minimum total movement.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu	Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Data communications devices, application studies resulting in better multiple-processor systems, reconfigurable hardware, wireless systems, special-purpose and application-based systems, adaptable architectures, heterogeneous (hybrid) systems, design studies, signal processing systems
1	Ivan Blunno, Luciano Lavagno	Designing an asynchronous microcontroller using Pipefitter.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Kanad Chakraborty	Testing and Reliability Techniques for High-Bandwidth Embedded RAMs.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	multiport RAM, BIST (built-in self-test), BISR (built-in self-repair), column-multiplexed addressing, fault tolerance, reliability, bandwidth
1	Michele Borgatti, L. Cali, Guido De Sandre, B. Forét, D. Iezzi, Francesco Lertora, G. Muzzi, Marco Pasotti, Marco Poles, Pier Luigi Rolandi	A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory.	DAC	2003	DBLP DOI BibTeX RDF	field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), reconfigurable architectures, integrated circuit design, multimedia computing, digital signal processors
1	Gregor Papa, Jurij Silc	Concurrent Operation Scheduling and Unit Allocation with an Evolutionary Technique.	DSD	2003	DBLP DOI BibTeX RDF
1	Mario Alberto Garcia Martinez, Guillermo Morales-Luna, Francisco Rodríguez-Henríquez	Hardware Implementation of the Binary Method for Exponentiation in GF(2m).	ENC	2003	DBLP DOI BibTeX RDF
1	Behrooz Zahiri	Structured ASICs: Opportunities and Challenges.	ICCD	2003	DBLP DOI BibTeX RDF
1	Gleb A. Chuvpilo, Saman P. Amarasinghe	High-Bandwidth Packet Switching on the Raw General-Purpose Architecture.	ICPP	2003	DBLP DOI BibTeX RDF
1	Chen Chang, Kimmo Kuusilinna, Brian C. Richards, Allen Chen, Nathan Chan, Robert W. Brodersen, Borivoje Nikolic	Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
1	Nikil D. Dutt, Kiyoung Choi	Configurable Processors for Embedded Computing.	IEEE Computer	2003	DBLP DOI BibTeX RDF
1	Pasquale Cocchini	A methodology for optimal repeater insertion in pipelined interconnects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Yuejian Wu, Paul N. MacDonald	Testing ASICs with multiple identical cores.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Amit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska	PITIA: an FPGA for throughput-intensive applications.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Rolf Drechsler, Nicole Drechsler	GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages.	EvoWorkshops	2003	DBLP DOI BibTeX RDF
1	Byeong Kil Lee, Lizy Kurian John	Implications of Programmable General Purpose Processors for Compression/Encryption Applications.	ASAP	2002	DBLP DOI BibTeX RDF
1	Ivan Blunno, Luciano Lavagno	Designing an Asynchronous Microcontroller Using Pipefitter.	ICCD	2002	DBLP DOI BibTeX RDF
1	Keith S. Vallerio, Niraj K. Jha	Task graph transformation to aid system synthesis.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Jiong Luo, Niraj K. Jha	Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems.	VLSI Design	2002	DBLP DOI BibTeX RDF	scheduling, real-time systems, embedded systems, low-power
1	Murali Kudlugi, Russell Tessier	Static scheduling of multidomain circuits for fast functional verification.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Oscal T.-C. Chen, R. R.-B. Sheen, S. Wang	A low-power adder operating on effective dynamic data ranges.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Wei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh	Design Tools for Application Specific Embedded Processors.	EMSOFT	2002	DBLP DOI BibTeX RDF
1	Sudhakar Yalamanchili	The Customization Landscape for Embedded Systems.	HiPC	2002	DBLP DOI BibTeX RDF
1	Hannu Tenhunen, Elena Dubrova	SoC Masters: An International M.Sc. Program in System-on-Chip Design at KTH. (PDF / PS)	MSE	2001	DBLP DOI BibTeX RDF
1	Christophe Bobda, Nils Steenbock	Singular Value Decomposition on Distributed Reconfigurable Systems.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF
1	Vishal Dalal, C. P. Ravikumar	Software Power Optimizations In An Embedded System.	VLSI Design	2001	DBLP DOI BibTeX RDF
1	Margarida F. Jacome, Helvio P. Peixoto	A Survey of Digital Design Reuse.	IEEE Design & Test of Computers	2001	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha	TAO: regular expression-based register-transfer level testability analysis and optimization.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl	Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI).	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Sharad Malik	Embedded Software Implementation Tools for Fully Programmable Application Specific Systems.	EMSOFT	2001	DBLP DOI BibTeX RDF
1	Russell Tessier, Wayne Burleson	Reconfigurable Computing for Digital Signal Processing: A Survey.	VLSI Signal Processing	2001	DBLP DOI BibTeX RDF	FPGA, survey, signal processing, reconfigurable computing
1	Ameet Bagwe, Rubin A. Parekhji	Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	fault coverage enhancement, embedded core based systems, test constraints, Texas Instruments TMS320C27xx, memory wrapper logic, fault diagnosis, logic testing, integrated circuit testing, application specific integrated circuits, functional testing, digital signal processing chips, fault analysis
1	F. Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu	DFT closure.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	area requirement, power requirement, timing closure flow, logic testing, SoC, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, ASIC, testability
1	Andrzej Hlawiczka, Michal Kopec	Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	serial seeding, linear hybrid cellular automata, n-cell CA register, p CdSR registers, cellular automata quasi shift register, PCASR, n-bit input sequence, logic testing, cellular automata, integrated circuit testing, automatic test pattern generation, application specific integrated circuits, polynomials, polynomial, logic CAD, cost, TPG, flip-flops, flip-flops, shift registers, pattern generators, integrated circuit economics
1	Kuen-Jong Lee, Cheng-I. Huang	A hierarchical test control architecture for core based design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	hierarchical test control architecture, SOC design, IEEE P1500 Working Group, test standard, IEEE 1149.1 cores, parallel testing capabilities, hierarchical test control mechanism, deeply embedded cores, hierarchical test access, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, IEEE standards, test architecture, core based design
1	Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen	Peak-power reduction for multiple-scan circuits during test application.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	peak-power reduction, multiple scan chain based circuits, peak periodicity, peak width, power waveforms, scan-based circuits, delay buffers, interleaving scan technique, data output, logic testing, logic testing, delays, integrated circuit testing, application specific integrated circuits, SOC, boundary scan testing
1	Ruofan Xu, Michael S. Hsiao	Embedded core testing using genetic algorithms.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	gate level implementation, user defined logic, random inputs, high level benchmarks, wrapper size, genetic algorithms, genetic algorithms, fault diagnosis, logic testing, controllability, controllability, high level synthesis, automatic test pattern generation, observability, observability, application specific integrated circuits, fault coverage, SOC, test application time, test patterns, embedded core testing, internal state
1	Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan	Buffer Assignment Algorithms on Data Driven ASICs.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	throughput, Application specific integrated circuits, buffers, data flow graph, wave-pipelining, data driven architecture
1	David G. Chinnery, Kurt Keutzer	Closing the gap between ASIC and custom: an ASIC perspective.	DAC	2000	DBLP DOI BibTeX RDF	custom, ASIC, comparison, clock frequency, clock speed
1	Amit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska	A novel high throughput reconfigurable FPGA architecture.	FPGA	2000	DBLP DOI BibTeX RDF
1	Romain Kamdem, Alain Fonkoua	Coprocessor Synthesis of Multirate System Using Static Scheduling Theory. (PDF / PS)	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	scheduling, real time, Codesign, codesign, hardware/software partitioning, target architecture