Search results for "application-specific processor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	P. Dang	High Performance Architecture of an Application Specific Processor for the H.264 Deblocking Filter.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Peter R. Cappello	Application-specific Processor Architecture: Then and Now.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	field-programmable gate array, FPGA, computer architecture, taxonomy, systolic array, processor array, application-specific processor, general-purpose processor
2	Marco Bera, Giovanni Danese, Francesco Leporati, Alvaro Spelgatti	A new technique to calculate dipolar energy and its implementation onto an application specific processor.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	Montecarlo simulations, FPGA, acceleration, application specific processors
2	Lorenzo Verdoscia	CODACS Project: A Development Tool for Embedded System Prototyping.	ICESS	2004	DBLP DOI BibTeX RDF	Application Specific Processor (ASP), FPGA, embedded system, functional programming, dataflow computing
2	Anteneh Alemu Abbo	An Embedded Processor for Integrated Navigation Receiver.	VLSI Design	1998	DBLP DOI BibTeX RDF	Integrated Navigation, Embedded Systems, FIR Filter, Application-Specific Processor
2	Andrew Wolfe, John Paul Shen	Flexible processors: a promising application-specific processor design approach.	MICRO	1988	DBLP DOI BibTeX RDF
1	Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar	Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng	Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP).	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Teemu Pitkänen, Jarmo Takala	Low-Power Application-Specific Processor for FFT Computations.	Signal Processing Systems	2011	DBLP DOI BibTeX RDF
1	J. Agustín Rodriguez, Omar D. Lifschitz, Víctor Manuel Jimenez-Fernandez, Pedro Julian, Osvaldo E. Agamennoni	Application-Specific Processor for Piecewise Linear Functions Computation.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Tobias G. Noll, Thorsten von Sydow, Bernd Neumann, Jochen Schleifer, Thomas Coenen, Götz Kappen	Reconfigurable Components for Application-Specific Processor Architectures.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
1	Achim Nohl, Frank Schirrmeister, Drew Taussig	Application specific processor design: Architectures, design methods and tools.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Philip P. Dang	Architecture of an application-specific processor for real-time implementation of H.264/AVC sub-pixel interpolation.	J. Real-Time Image Processing	2009	DBLP DOI BibTeX RDF
1	Stefan Eberli, Andreas Burg, Wolfgang Fichtner	Implementation of a 2×2 MIMO-OFDM receiver on an application specific processor.	Microelectronics Journal	2009	DBLP DOI BibTeX RDF
1	Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs).	SAMOS	2009	DBLP DOI BibTeX RDF
1	Teemu Pitkänen, Jarmo Takala	Low-power application-specific processor for FFT computations.	ICASSP	2009	DBLP DOI BibTeX RDF
1	Andreas Genser, Christian Bachmann, Christian Steger, Jos Hulzink, Mladen Berekovic	Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing.	ASAP	2009	DBLP DOI BibTeX RDF
1	Tero Rintaluoma, Timo Reinikka, Joona Rouvinen, Jani Boutellier, Pekka Jääskeläinen, Olli Silvén	Programmable Accelerators for Reconfigurable Video Decoder.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Zhijie Jerry Shi, Xiao Yang, Ruby B. Lee	Alternative application-specific processor architectures for fast arbitrary bit permutations.	IJES	2008	DBLP DOI BibTeX RDF
1	Lars Bauer, Muhammad Shafique, Jörg Henkel	Run-time instruction set selection in a transmutable embedded processor.	DAC	2008	DBLP DOI BibTeX RDF	extensible embedded processors, special instruction, reconfigurable computing, ASIP, run-time adaptation
1	Christophe Wolinski, Krzysztof Kuchcinski	Automatic Selection of Application-Specific Reconfigurable Processor Extensions.	DATE	2008	DBLP DOI BibTeX RDF
1	Nikolaos Kavvadias, Spiridon Nikolaidis	Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Optimization, Microprocessors, Hardware description languages, Real-time and embedded systems, Pipeline processors, Control design
1	Hans Vandierendonck, Koen De Bosschere	Constructing Optimal XOR-Functions to Minimize Cache Conflict Misses.	ARCS	2008	DBLP DOI BibTeX RDF
1	Giovanni Danese, Francesco Leporati, Marco Bera, Mauro Giachero, Nelson Nazzicari, Alvaro Spelgatti	An Application Specific Processor for Montecarlo Simulations.	PDP	2007	DBLP DOI BibTeX RDF
1	Thomas Y. Yeh, Petros Faloutsos, Sanjay J. Patel, Glenn Reinman	ParallAX: an architecture for real-time physics.	ISCA	2007	DBLP DOI BibTeX RDF	real-time physics, chip multiprocessor, physics based animation, stream processing, interactive entertainment, application specific processor
1	Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, Rami G. Melhem	CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications.	ISPASS	2007	DBLP DOI BibTeX RDF	high-performance search accelerator, high-performance memory substrate, search-intensive application, content addressable random access memory, search operation, memory hierarchy concept, direct hardware implementation, parallel key matching operation, hash function, memory access, application-specific processor, memory structure, hashing technique
1	Tirath Ramdas, Gregory K. Egan, David Abramson, Kim Baldridge	Converting massive TLP to DLP: a special-purpose processor for molecular orbital computations.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	thread-level parallelism, content-addressable memory, vector processing, address generation, data-level parallelism
1	Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Design space exploration of partially re-configurable embedded processors.	DATE	2007	DBLP DOI BibTeX RDF
1	Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	ASIP architecture exploration for efficient IPSec encryption: A case study.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	computer-aided design, ADL, ASIP, IPSec
1	Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson	An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data Sets.	ASAP	2006	DBLP DOI BibTeX RDF
1	Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah, Daniel Gajski	Generic netlist representation for system and PE level design exploration.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	GNR, NISC, modeling, synthesis, system design, architecture description language, application-specific processor
1	Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa	High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core.	The Journal of Supercomputing	2006	DBLP DOI BibTeX RDF	queue processor, design, prototyping, high performance, high-level modeling
1	Olaf Lüthje	A methodology for automated analysis of application specific processor models with respect to test generation.		2005	RDF
1	Teemu Pitkänen, Tommi Rantanen, Andrea G. M. Cilio, Jarmo Takala	Hardware Cost Estimation for Application-Specific Processor Design.	SAMOS	2005	DBLP DOI BibTeX RDF
1	Andreas Hoffmann, Frank Fiedler, Achim Nohl, Surender Parupalli	A Methodology and Tooling Enabling Application Specific Processor Design.	VLSI Design	2005	DBLP DOI BibTeX RDF	SIMD, VLIW, ASIP
1	Masayuki Masuda, Kazuhito Ito	Rapid and precise instruction set evaluation for application specific processor design.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Earl E. Swartzlander Jr.	Three Dimensional System on Chip Technology, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
1	Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran	Rapid Embedded Hardware/Software System Generation.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Allen C. Cheng, Gary S. Tyson	An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Low-power design, reconfigurable hardware, real-time and embedded systems, energy-aware systems, instruction set design
1	Ben A. Abderazek, Sotaro Kawata, Tsutomu Yoshinaga, Masahiro Sowa	Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core.	EUC	2005	DBLP DOI BibTeX RDF
1	Timothy Sherwood, Mark Oskin, Brad Calder	Balancing design options with Sherpa.	CASES	2004	DBLP DOI BibTeX RDF	peicewise linear model, computer architecture, design space exploration, application specific processor (ASIP), area minimization
1	Allen C. Cheng, Gary S. Tyson, Trevor N. Mudge	FITS: framework-based instruction-set tuning synthesis for embedded application specific processors.	DAC	2004	DBLP DOI BibTeX RDF	16-bit ISA, instruction synthesis, low-power, energy efficient, embedded processor, reconfigurable processors, ASP, instruction encoding, configurable architecture, code density
1	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	A Scalable Application-Specific Processor Synthesis Methodology.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Nathan Clark, Hongtao Zhong, Wilkin Tang, Scott A. Mahlke	Automatic Design of Application Specific Instruction Set Extensions Through Dataflow Graph Exploration.	International Journal of Parallel Programming	2003	DBLP DOI BibTeX RDF	hardware customization, embedded system, instruction set, application-specific processor, dataflow graph
1	Wei Qin, Sharad Malik	Automated synthesis of efficient binary decoders for retargetable software toolkits.	DAC	2003	DBLP DOI BibTeX RDF	binary decoder, decoding tree, decision tree, instruction set simulator
1	Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke	Systematic Register Bypass Customization for Application-Specific Processors.	ASAP	2003	DBLP DOI BibTeX RDF
1	Gokhan Memik, William H. Mangione-Smith	A flexible accelerator for layer 7 networking applications.	DAC	2002	DBLP DOI BibTeX RDF	pattern matching, network processor, accelerator, table lookup, application-specific processor, networking applications
1	Christopher T. Weaver, Rajeev Krishna, Lisa Wu, Todd M. Austin	Application specific architectures: a recipe for fast, flexible and power efficient designs.	CASES	2001	DBLP DOI BibTeX RDF
1	Michael Gschwind, Valentina Salapura, D. Maurer	FPGA prototyping of a RISC processor core for embedded applications.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Frank A. Engel, Johannes Nührenberg, Gerhard Fettweis	A generic tool set for application specific processor architectures.	CODES	2000	DBLP DOI BibTeX RDF
1	Hyesook Lim, Vincenzo Piuri, Earl E. Swartzlander Jr.	A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Application specific processor architecture, Inverse Discrete Cosine Transform, serial-parallel processor, image compression, Discrete Cosine Transform, systolic array
1	Margarida F. Jacome, Gustavo de Veciana	Design Challenges for New Application-Specific Processors.	IEEE Design & Test of Computers	2000	DBLP DOI BibTeX RDF
1	Miodrag Potkonjak, Wayne Wolf	A methodology and algorithms for the design of hard real-time multitasking ASICs.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF
1	Bruce R. Childers, Jack W. Davidson	Architectural Considerations for Application-Specific Counterflow Pipelines.	ARVLSI	1999	DBLP DOI BibTeX RDF	Application-specific integrated processors, counterflow pipelines, architectural synthesis
1	José Carlos Alves, José Silva Matos	RVC - A Reconfigurable Coprocessor for Vector Processing Applications.	FCCM	1998	DBLP DOI BibTeX RDF
1	Ireneusz Karkowski, Henk Corporaal	Design of Heterogenous Multi-Processor Embedded Systems: Applying Functional Pipelining.	IEEE PACT	1997	DBLP DOI BibTeX RDF	heterogenous multiprocessor embedded system design, functional pipelining, embedded program mapping, ANSI C program, application specific processor pipeline, frequency tracking system, two-processor system, highly optimized single core solution, architecture, multiprocessing systems, instruction level parallelism, speedup, efficient algorithm, loops
1	Patrick M. Lenders, Sanjay V. Rajopadhye	Multirate VLSI Arrays and Their Synthesis.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	Application specific processor arrays, index transformations, VLSI signal processing, systolic arrays, space-time mappings
1	Ehat Ercanli, Christos A. Papachristou	A Register File and Scheduling Model for Application Specific Processor Synthesis.	DAC	1996	DBLP DOI BibTeX RDF
1	Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata	Digit On-line Large Radix CORDIC Rotator.	ASAP	1995	DBLP DOI BibTeX RDF	Digit on-line processing, Pipelined array architecture, VLSI architecture, Application-specific processor, CORDIC algorithm
1	Eric Aardoom, Paul Stravers	An Application Specific Processor for a Multi-System Navigation Receiver.	ICCD	1992	DBLP BibTeX RDF
1	Mauricio Breternitz Jr., John Paul Shen	Architecture Synthesis of High-Performance Application-Specific Processors.	DAC	1990	DBLP DOI BibTeX RDF
1	J. M. Mulder, R. J. Portier, A. Srivastava	A framework for high-speed controller design.	MICRO	1990	DBLP DOI BibTeX RDF
1	J. M. Mulder, R. J. Portier, A. Srivastava, R. in 't Velt	An Architecture Framework for Application-Specific and Scalable Architectures.	ISCA	1989	DBLP DOI BibTeX RDF
1	Hans Mulder, P. Stravers	A flexible VLSI core for an adaptable architecture.	MICRO	1989	DBLP DOI BibTeX RDF
1	Andrew Wolfe, Mauricio Breternitz Jr., Chriss Stephens, A. L. Ting, D. B. Kirk, Ronald P. Bianchini Jr., John Paul Shen	The White Dwarf: A High-Performance Application-Specific Processor.	ISCA	1988	DBLP BibTeX RDF