Search results for "architecture exploration"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Praveen Raghavan, Murali Jayapala, Andy Lambrechts, Javed Absar, Francky Catthoor	Playing the trade-off game: Architecture exploration using Coffeee.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	design, embedded systems, Energy, VLIW, processors, power estimation, loop transformations, architecture exploration, area, power-performance trade-off, compiler-architecture interaction
3	Nikos S. Voros, Konstantinos Masselos	Prototyping of a WLAN system using C++ based architecture exploration.	MobiMedia	2007	DBLP DOI BibTeX RDF	hardware/software codesign, wireless systems, architecture exploration
3	Marius Bonaciu, Aimen Bouchhima, Mohamed-Wassim Youssef, Xi Chen, Wander O. Cesário, Ahmed Amine Jerraya	High-level architecture exploration for MPEG4 encoder with custom parameters.	ASP-DAC	2006	DBLP DOI BibTeX RDF	multiprocessors SOC architecture, customization, video encoder, architecture exploration, MPEG4
3	Junyu Peng, Samar Abdi, Daniel Gajski	Automatic Model Refinement for Fast Architecture Exploration.	VLSI Design	2002	DBLP DOI BibTeX RDF	architecture exploration, model refinement
2	Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Pre- and postfabrication architecture exploration for partially reconfigurable VLIW processors.	ACM Trans. Embedded Comput. Syst.	2009	DBLP DOI BibTeX RDF	coarse-grained FPGA, VLIW, ASIP
2	Zhongbo Cao, Ramon Mercado, Diane T. Rover	System-level memory modeling for bus-based memory architecture exploration.	EIT	2009	DBLP DOI BibTeX RDF
2	Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors.	ACM Trans. Embedded Comput. Syst.	2008	DBLP DOI BibTeX RDF	coarse-grained FPGA, VLIW, ASIP
2	Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid	A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Ian Kuon, Jonathan Rose	Automated transistor sizing for FPGA architecture exploration.	DAC	2008	DBLP DOI BibTeX RDF	optimization, FPGA, transistor sizing
2	T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan	Memory Architecture Exploration Framework for Cache Based Embedded SOC.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	Sungchan Kim, Chanik Park, Soonhoi Ha	Architecture Exploration of NAND Flash-based Multimedia Card.	DATE	2008	DBLP DOI BibTeX RDF
2	Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	ASIP architecture exploration for efficient IPSec encryption: A case study.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	computer-aided design, ADL, ASIP, IPSec
2	Paolo Giusto, Sri Kanajan, Claudio Pinello, Max Chiodo	A Conceptual Data Model for the Architecture Exploration of Automotive Distributed Embedded Architectures.	IRI	2007	DBLP DOI BibTeX RDF
2	Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
2	Matti Eteläperä, Janne Vatjus Anttila, Juha Pekka Soinimen	Architecture Exploration of 3D Video Recorder Using Virtual Platform Models.	DSD	2007	DBLP DOI BibTeX RDF
2	T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan	MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Patrice Gerin, Hao Shen, A. Chureau, Aimen Bouchhima, Ahmed Amine Jerraya	Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemC.	ASP-DAC	2007	DBLP DOI BibTeX RDF	transaction accurate level, hardware/software interface modeling, multiprocessor SoC design, automatic generation tools, system-on-chip, SystemC, abstraction level, architecture exploration
2	Konstantinos Masselos, Kari Tiensyrjä, Yang Qu, Nikos S. Voros, Miroslav Cupák, Luc Rijnders, Marko Pettissalo	System Level Architecture Exploration for Reconfigurable Systems On Chip.	FPL	2006	DBLP DOI BibTeX RDF
2	Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
2	Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar	Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC.	DAC	2006	DBLP DOI BibTeX RDF	computation offloading, software partitioning
2	Ingolf H. Krüger, Gunny Lee, Michael Meisinger	Automating software architecture exploration with M2Aspects.	SCESM	2006	DBLP DOI BibTeX RDF	architecture comparison, distributed reactive systems, software architecture exploration, components, aspect-oriented programming, services, scenarios, roles, aspects, AspectJ
2	Guang-Sheng Ma, Xiuqin Wang, Hao Wang	Web-Based Cooperative Design for SoC and Improved Architecture Exploration Algorithm.	APWeb Workshops	2006	DBLP DOI BibTeX RDF
2	Tero Kangas, Petri Kukkala, Heikki Orsila, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Jouni Riihimäki, Kimmo Kuusilinna	UML-based multiprocessor SoC design framework.	ACM Trans. Embedded Comput. Syst.	2006	DBLP DOI BibTeX RDF	design flow, architecture exploration, UML 2.0
2	Bingfeng Mei, Andy Lambrechts, Diederik Verkest, Jean-Yves Mignolet, Rudy Lauwereins	Architecture Exploration for a Reconfigurable Architecture Template.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF
2	Ivano Barbieri, Massimo Bariani, Alberto Cabitto, Marco Raggio	A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures.	VLSI Signal Processing	2005	DBLP DOI BibTeX RDF	Hw-Sw co-design, simulation speed, simulation accuracy, simulation, multimedia, system on chip, DSP, flexibility, VLIW, architecture exploration, ISA
2	Paolo Martinelli, Armin Wellig, Julien Zory	Transaction-Level Prototyping of a UMTS Outer-Modem for System-on-Chip Validation and Architecture Exploration.	IEEE International Workshop on Rapid System Prototyping	2004	DBLP DOI BibTeX RDF
2	Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study.	SCOPES	2004	DBLP DOI BibTeX RDF
2	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Extending the transaction level modeling approach for fast communication architecture exploration.	DAC	2004	DBLP DOI BibTeX RDF	bus cycle accurate modeling, communication architecture exploration, shared bus architectures, transaction level modeling, AMBA
2	Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl	RTL Processor Synthesis for Architecture Exploration and Implementation.	DATE	2004	DBLP DOI BibTeX RDF
2	Hye-On Jang, Minsoo Kang, Myeong-jin Lee, Kwanyeob Chae, Kookpyo Lee, Kyuhyun Shim	High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study.	DATE	2004	DBLP DOI BibTeX RDF
2	Peter Grun, Nikil D. Dutt, Alexandru Nicolau	Access pattern-based memory and connectivity architecture exploration.	ACM Trans. Embedded Comput. Syst.	2003	DBLP DOI BibTeX RDF	Memory, access patterns, architecture exploration
2	George Hadjiyiannis, Srinivas Devadas	Techniques for accurate performance evaluation in architecture exploration.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
2	Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr	Instruction encoding synthesis for architecture exploration using hierarchical processor models.	DAC	2003	DBLP DOI BibTeX RDF	instruction set architectures, instruction encoding
2	Thomas Wild, Jürgen Foag, Nuria Pazos, Winthir Brunnbauer	Mapping and Scheduling for Architecture Exploration of Networking SoCs.	VLSI Design	2003	DBLP DOI BibTeX RDF
2	Silvia Brini, Doha Benjelloun, Fabien Castanier	A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL Modems.	DATE	2003	DBLP DOI BibTeX RDF
2	Oliver Wahlen, Tilman Glökler, Achim Nohl, Andreas Hoffmann, Rainer Leupers, Heinrich Meyr	Application specific compiler/architecture codesign: a case study.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	ASIP, architecture exploration, retargetable compiler
2	Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya	Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems.	IEEE Trans. Software Eng.	2002	DBLP DOI BibTeX RDF	hardware/software codesign, Performance estimation, multiprocessor architectures, architecture exploration, system-level simulation
2	Lukai Cai, Daniel Gajski, Mike Olivarez	Introduction of system level architecture exploration using the SpecC methodology.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Salvador Mir, Benoît Charlot, Gabriela Nicolescu, Philippe Coste, Fabien Parrain, Nacer-Eddine Zergainoh, Bernard Courtois, Ahmed Amine Jerraya, Márta Rencz	Towards design and validation of mixed-technology SOCs.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF	design, verification, MEMS, SOCs, architecture exploration, HDLs, cosimulation
1	T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar	On-chip memory architecture exploration framework for DSP processor-based embedded system on chip.	ACM Trans. Embedded Comput. Syst.	2012	DBLP DOI BibTeX RDF
1	Jean-Jacques Lecler, Gilles Baillieu	Application driven network-on-chip architecture exploration & refinement for a complex SoC.	Design Autom. for Emb. Sys.	2011	DBLP DOI BibTeX RDF
1	Young-Pyo Joo, Sungchan Kim, Soonhoi Ha	Fast Communication Architecture Exploration of Processor Pool-Based MPSoC via Static Performance Analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, Kenneth B. Kent, Jonathan Rose	VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling.	TRETS	2011	DBLP DOI BibTeX RDF
1	Zhen Wang, Ding Xie, Jinmei Lai	FPGA Interconnect Architecture Exploration Based on a Statistical Model.	FPL	2011	DBLP DOI BibTeX RDF	hops, model, FPGA, interconnect
1	Mahmoud Momtazpour, Mahboobeh Ghorbani, Maziar Goudarzi, Esmaeil Sanaei	Simultaneous variation-aware architecture exploration and task scheduling for MPSoC energy minimization.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Chao-Lieh Chen, Li-Shin Chuo, Wu-Liang Cheng, Chun-Ching Wu, Chien-Hao Lai	Architecture exploration of QoS control Silicon Intellectual Properties for Cross-Layer Designs in wireless networks.	ICME	2011	DBLP DOI BibTeX RDF
1	Mona Safar, Magdy A. El-Moursy, Ashraf Salem, Mohamed AbdElSalam	TLM Based Approach for Architecture Exploration of Multicore Systems-on-Chip.	MTV	2011	DBLP DOI BibTeX RDF
1	Sung-Rok Yoon, Min Li Huang, Sang-Ho Seo, Hiroshi Ochi, Sin-Chong Park	A Fast Architecture Exploration Method for High Throughput IEEE 802.11e MAC Implementation Using SystemC.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Dong Kim, Kwanhu Bang, Seung-Hwan Ha, Sungroh Yoon, Eui-Young Chung	Architecture Exploration of High-Performance PCs with a Solid-State Disk.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	dual-port DRAM, North Bridge, direct path, NAND flash memory, Solid-State Disk (SSD)
1	Rosilde Corvino, Abdoulaye Gamatié, Pierre Boulet	Architecture Exploration for Efficient Data Transfer and Storage in Data-Parallel Applications.	Euro-Par	2010	DBLP DOI BibTeX RDF
1	Fatemeh Javaheri, Zainalabedin Navabi	ESL design methodology for architecture exploration.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Soongyu Kwon, Dongjae Song, Seung Wook Lee, Jong Tae Kim	System Level Power Analysis for SoC Architecture Exploration.	PDPTA	2010	DBLP BibTeX RDF
1	Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato	A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation.	SoCC	2010	DBLP DOI BibTeX RDF
1	Benedikt Huber, Wolfgang Puffitsch, Martin Schoeberl	WCET driven design space exploration of an object cache.	JTRES	2010	DBLP DOI BibTeX RDF
1	Lih-Yih Chiou, Yi-Siou Chen, Chih-Hsien Lee	System-Level Bus-Based Communication Architecture Exploration Using a Pseudoparallel Algorithm.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Jonathan Rose	The evolution of architecture exploration of programmable devices.	FPL	2009	DBLP DOI BibTeX RDF
1	Chafic Jaber, Andreas Kanstein, Ludovic Apvrille, Amer Baghdadi, Patricia Le Moenner, Renaud Pacalet	High-Level System Modeling for Rapid HW/SW Architecture Exploration.	IEEE International Workshop on Rapid System Prototyping	2009	DBLP DOI BibTeX RDF
1	Timo Schönwald, Jochen Zimmermann, Oliver Bringmann, Wolfgang Rosenstiel	Network-on-Chip Architecture Exploration Framework.	DSD	2009	DBLP DOI BibTeX RDF
1	Andreas Genser, Christian Bachmann, Christian Steger, Jos Hulzink, Mladen Berekovic	Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing.	ASAP	2009	DBLP DOI BibTeX RDF
1	Khaled Rahmouni, Patrice Gerin, Sebastien Chabanet, Paul Pianu, Frédéric Pétrot	Modelling and architecture exploration of a medium voltage protection device.	SIES	2009	DBLP DOI BibTeX RDF
1	Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, Jonathan Rose	VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, architecture, cad
1	Mahdi Elghazali, Ahmed Elhossini, Shawki Areibi	HW/SW co-design architecture exploration for VLSI maze routing.	CCECE	2009	DBLP DOI BibTeX RDF
1	Martin Lukasiewycz, Martin Streubühr, Michael Glaß, Christian Haubelt, Jürgen Teich	Combined system synthesis and communication architecture exploration for MPSoCs.	DATE	2009	DBLP BibTeX RDF
1	Young-Pyo Joo, Sungchan Kim, Soonhoi Ha	On-chip communication architecture exploration for processor-pool-based MPSoC.	DATE	2009	DBLP BibTeX RDF
1	Guo-An Jian, Jui-Chin Chu, Ting-Yu Huang, Tao-Cheng Chang, Jiun-In Guo	A System Architecture Exploration on the Configurable HW/SW Co-design for H.264 Video Decoder.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung	Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep.	ARC	2009	DBLP DOI BibTeX RDF	FPGA, Reconfigurable architectures, Floorplanning, integer linear programming (ILP)
1	Stefana Nenova, Daniel Kästner	Worst-Case Timing Estimation and Architecture Exploration in Early Design Phases.	WCET	2009	DBLP BibTeX RDF
1	Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Toshio Isomura, Kazuo Satou	Trace-driven workload simulation method for Multiprocessor System-On-Chips.	DAC	2009	DBLP DOI BibTeX RDF	MPSoC architecture exploration, simulation, performance estimation, workload model
1	David Novo, Thomas Schuster, Bruno Bougard, Andy Lambrechts, Liesbet Van der Perre, Francky Catthoor	Energy-performance Exploration of a CGA-based SDR Processor.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Coarse grain arrays, SDR terminals, Low power, Architecture exploration
1	Patrice Gerin, Mian Muhammad Hamayun, Frédéric Pétrot	Native MPSoC co-simulation environment for software performance estimation.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	code annotation, MPSoC, system simulation, cross-compilation
1	Alon Gluska, Lior Libis	Shortening the verification cycle with synthesizable abstract models.	DAC	2009	DBLP DOI BibTeX RDF	verification, logic design, abstract modeling
1	Zhonglei Wang, Andreas Herkersdorf, Wolfgang Haberl, Martin Wechs	SysCOLA: a framework for co-development of automotive software and system platform.	DAC	2009	DBLP DOI BibTeX RDF	COLA, SystemC, system modeling, virtual prototyping
1	Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	A SIMD optimization framework for retargetable compilers.	TACO	2009	DBLP DOI BibTeX RDF	SIMD, vectorization, ASIP, subword parallelism, retargetable compilers
1	François Verdier, Benoit Miramond, Mickaël Maillard, Emmanuel Huck, Thomas LeFebvre	Using High-Level RTOS Models for HW/SW Embedded Architecture Exploration: Case Study on Mobile Robotic Vision.	EURASIP J. Emb. Sys.	2008	DBLP DOI BibTeX RDF
1	Yifan He, Zoran Zivkovic, Richard P. Kleihorst, Alexander Danilin, Henk Corporaal, Bart Mesman	Real-Time Hough Transform on 1-D SIMD Processors: Implementation and Architecture Exploration.	ACIVS	2008	DBLP DOI BibTeX RDF
1	Hao Shen, Patrice Gerin, Frédéric Pétrot	Configurable Heterogeneous MPSoC Architecture Exploration Using Abstraction Levels.	IEEE International Workshop on Rapid System Prototyping	2008	DBLP DOI BibTeX RDF
1	Alena Simalatsar, Roberto Passerone, Douglas Densmore	A methodology for architecture exploration and performance analysis using system level design languages and rapid architecture profiling.	SIES	2008	DBLP DOI BibTeX RDF
1	Vinod Kathail, Tom Miller	Architecture Exploration for Low Power Design.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Hao Shen, Frédéric Pétrot	MPSoC Communication Architecture Exploration Using an Abstraction Refinement Method.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Per Gunnar Kjeldsberg, Francky Catthoor, Sven Verdoolaege, Martin Palkovic, Arnout Vandecappelle, Qubo Hu, Einar J. Aas	Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	Memory architecture exploration, High level synthesis, Memory optimization, Multi-media, Code transformation
1	Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh	Retargetable Code Optimization for Predicated Execution.	DATE	2008	DBLP DOI BibTeX RDF
1	Arvind, Rishiyur S. Nikhil	Hands-on Introduction to Bluespec System Verilog (BSV) (Abstract).	MEMOCODE	2008	DBLP DOI BibTeX RDF
1	Abel G. Silva-Filho, Sidney M. L. Lima	Energy consumption reduction mechanism by tuning cache configuration usign NIOS II processor.	SoCC	2008	DBLP DOI BibTeX RDF
1	Tarek M. Taha, D. Scott Wills	An Instruction Throughput Model of Superscalar Processors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Modeling techniques, Pipeline processors, Modeling of computer architecture
1	Praveen Raghavan, Andy Lambrechts, Javed Absar, Murali Jayapala, Francky Catthoor, Diederik Verkest	Coffee: COmpiler Framework for Energy-Aware Exploration.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Lobna Kriaa, Aimen Bouchhima, Marius Gligor, Anne-Marie Fouillart, Frédéric Pétrot, Ahmed Amine Jerraya	Parallel Programming of Multi-processor SoC: A HW-SW Interface Perspective.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	HW/SW interfaces, Programming models, heterogeneous MPSoC
1	Hyung Gyu Lee, Naehyuck Chang, Ümit Y. Ogras, Radu Marculescu	On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	MPEG-2 encoder, system-on-chip, Networks-on-chip, FPGA prototype, point-to-point
1	Simon Giesecke, Johannes Bornhold, Wilhelm Hasselbring	Middleware-Induced Architectural Style Modelling for Architecture Exploration.	WICSA	2007	DBLP DOI BibTeX RDF
1	Rahul Jain, Preeti Ranjan Panda	Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Hyun-min Kyung, Gi-Ho Park, Jong Wook Kwak, WooKyeong Jeong, Tae-Jin Kim, Sung-Bae Park	Performance monitor unit design for an AXI-based multi-core SoC platform.	SAC	2007	DBLP DOI BibTeX RDF	SOC platform, performance monitor, architecture exploration, AMBA, AXI
1	Qubo Hu, Per Gunnar Kjeldsberg, Arnout Vandecappelle, Martin Palkovic, Francky Catthoor	Incremental hierarchical memory size estimation for steering of loop transformations.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Data optimization, memory architecture exploration, memory size estimation, high-level synthesis, code transformation
1	Ismail Assayad, Sergio Yovine	Modelling and Exploration Environment for Application Specific Multiprocessor Systems.	HASE	2007	DBLP DOI BibTeX RDF	Software/Hardware Analysis, Architecture Exploration, Multiprocessor Embedded Systems
1	Anup Gangwar, M. Balakrishnan, Anshul Kumar	Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	performance evaluation, VLIW, ASIP, clustered VLIW processors
1	Andreas Lankes, Thomas Wild, Johannes Zeppenfeld	Power Estimation of Time Variant SoCs with TAPES.	DSD	2007	DBLP DOI BibTeX RDF
1	Fabiano Hessel, César A. M. Marcon, Tatiana Gadelha Serra dos Santos	High Level RTOS Scheduler Modeling for a Fast Design Validation.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Flavius Gruian, Mark Westmijze	BluEJAMM: A Bluespec Embedded Java Architecture with Memory Management.	SYNASC	2007	DBLP DOI BibTeX RDF
1	Takashi Kinoshima, Kazutaka Kobayashi, Nurul Azma Zakaria, Masahiro Kimura, Noriko Matsumoto, Norihiko Yoshida	Communication Model Exploration for Distributed Embedded Systems and System Level Interpretations.	EUC Workshops	2007	DBLP DOI BibTeX RDF	Event-Triggered Communication, Time-Triggered Communication, Stepwise Refinement Design, Model-Driven Architecture, Distributed Embedded Systems
1	Pongstorn Maidee, Kia Bazargan	Defect-Tolerant FPGA Architecture Exploration.	FPL	2006	DBLP DOI BibTeX RDF
1	Florian Stock, Andreas Koch	Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays.	FPL	2006	DBLP DOI BibTeX RDF