Search results for "architecture parameters"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Dennis B. Mulcare	System-level optimization of architectural performance under varying service demands.	ECBS	1996	DBLP DOI BibTeX RDF	system-level optimization, architectural performance, varying service demands, cost-performance measures, dynamic performance, varying workload, system resource parameters, architecture parameters, online transaction processing system, fitness metric, fitness ranking, multiple mutation operator mechanism, genetic algorithms, genetic algorithm, optimization, distributed processing, convergence, system design, systems analysis, performance measures, transaction processing, software performance evaluation, software prototyping, tolerances, online operation, chromosome, distributed system architectures
1	Joydip Das, Steven J. E. Wilton	An analytical model relating FPGA architecture parameters to routability.	FPGA	2011	DBLP DOI BibTeX RDF
1	Ricardo de A. Araújo, Adriano L. I. de Oliveira, Sérgio C. B. Soares	A covariance matrix adaptation based evolutionary methodology for phase adjustment in financial time series forecasting.	GECCO	2010	DBLP DOI BibTeX RDF	covariance matrix adaptation evolution strategy, multilayer perceptron networks, random walk dilemma, time phase adjustment, evolutionary algorithms, financial time series forecasting
1	Wei Mark Fang, Jonathan Rose	Modeling routing demand for early-stage FPGA architecture development.	FPGA	2008	DBLP DOI BibTeX RDF	model, FPGA, routing, architecture
1	Mingjie Lin, Abbas El Gamal	TORCH: a design tool for routing channel segmentation in FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, performance analysis, segmentation, routing architecture
1	Sungchan Kim, Chanik Park, Soonhoi Ha	Architecture Exploration of NAND Flash-based Multimedia Card.	DATE	2008	DBLP DOI BibTeX RDF
1	Archana Kalyansundar, Rita Chattopadhyay	A Novel Approach to Hardware Architecture Design and Advanced Optimization Techniques for Time Critical Applications.	EUC	2008	DBLP DOI BibTeX RDF
1	Sven F. Crone, Rohit Dhawan	Forecasting Seasonal Time Series with Neural Networks: A Sensitivity Analysis of Architecture Parameters.	IJCNN	2007	DBLP DOI BibTeX RDF
1	Wahid Nasri, Luiz Angelo Steffenel, Denis Trystram	Adaptive Performance Modeling on Hierarchical Grid Computing Environments.	CCGRID	2007	DBLP DOI BibTeX RDF
1	Wahid Nasri, Hajer Hamad, Hadhemi Fejjari	A Framework for Adaptive Communication Modeling on Heterogeneous Hierarchical Clusters.	CLUSTER	2006	DBLP DOI BibTeX RDF
1	Grigoris Dimitroulakos, Michalis D. Galanis, Constantinos E. Goutis	Resource constrained modulo scheduling for coarse-grained reconfigurable arrays.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Marco Macchetti, Wenyu Chen	ASIC hardware implementation of the IDEA NXT encryption algorithm.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Hangsheng Wang, Li-Shiuan Peh, Sharad Malik	A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks.	DATE	2005	DBLP DOI BibTeX RDF
1	Juan Rubio, Charles Lefurgy, Lizy Kurian John	Improving Server Performance on Transaction Processing Workloads by Enhanced Data Placement.	SBAC-PAD	2004	DBLP DOI BibTeX RDF
1	Krishna V. Palem, Lakshmi N. Chakrapani, Sudhakar Yalamanchili	A Framework for Compiler Driven Design Space Exploration for Embedded System Customization.	ASIAN	2004	DBLP DOI BibTeX RDF
1	Fei Li, Deming Chen, Lei He, Jason Cong	Architecture evaluation for power-efficient FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA power model, low power design, FPGA architecture
1	Lucian Codrescu, S. Nugent, James D. Meindl, D. Scott Wills	Modeling technology impact on cluster microprocessor performance.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon, Didier Demigny	A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring.	FPL	2003	DBLP DOI BibTeX RDF
1	Dirk Fischer, Jürgen Teich, Michael Thies, Ralph Weper	Efficient architecture/compiler co-exploration for ASIPs.	CASES	2002	DBLP DOI BibTeX RDF	architecture/compiler codesign, multiobjective design space exploration, ASIP, retargetable compilation
1	Casiano Rodríguez	The Design and Analysis of Parallel Algorithms.	PDP	2002	DBLP DOI BibTeX RDF
1	Yasemin Yalçinkaya, Trond Steihaug	An Analytical Model for a Class of Architectures under Master-Slave Paradigm.	HPCN	2000	DBLP DOI BibTeX RDF
1	Olivier Pasquier, Jean Paul Calvez	An Object-Based Executable Model for Simulation of Real-Time Hw/Sw Systems.	DATE	1999	DBLP DOI BibTeX RDF
1	Namseung Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, In-Cheol Park, Chong-Min Kyung	Virtual Chip: Making Functional Models Work on Real Target Systems.	DAC	1998	DBLP DOI BibTeX RDF	reconstruction, emulation, visibility, functional simulation
1	Joan García-Haro, Rocío Marín-Sillué, José Luis Melús-Moreno	ATMSWSIM An Efficient, Portable and Expandable ATM SWitch SIMulator Tool.	Computer Performance Evaluation	1994	DBLP DOI BibTeX RDF
1	Erol Gelenbe	Performance Analysis of the Connection Machine.	SIGMETRICS	1990	DBLP DOI BibTeX RDF