Search results for "architecture-level"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Jeffry T. Russell, Margarida F. Jacome	Architecture-level performance evaluation of component-based embedded systems.	DAC	2003	DBLP DOI BibTeX RDF	performance evaluation, embedded system, scenario, design space exploration, component-based, architecture-level
3	Rita Yu Chen, Mary Jane Irwin, Raminder Singh Bajwa	Architecture-level power estimation and design experiments.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	architecture tradeoff, architecture-level power estimation, control unit, energy table, instruction format transition, output signal transition, power analysis and estimation, switch capacitance, low power design, hardware/software codesign, energy model, functional unit, computer-aided design of VLSI
3	Helvio P. Peixoto, Margarida F. Jacome	Algorithm and architecture-level design space exploration using hierarchical data flows.	ASAP	1997	DBLP DOI BibTeX RDF	architecture-level design space exploration, algorithm-level design space exploration, hierarchical data flows, fidelity system-level metrics, systems analysis, power consumption
2	Zafar Mehboob, Didar Zowghi, David Lowe	An Approach for Comparison of Architecture Level Change Impact Analysis Methods and Their Relevance in Web Systems Evolution.	Australian Software Engineering Conference	2009	DBLP DOI BibTeX RDF
2	Ge Zhang, Xu Yang, Yiwei Zhang	Architecture Level Energy Modeling and Optimization for Multi-Ported Giga-Hz Physical Register File.	NAS	2009	DBLP DOI BibTeX RDF
2	Pradeep Ramachandran, Sarita V. Adve, Pradip Bose, Jude A. Rivers	Metrics for Architecture-Level Lifetime Reliability Analysis.	ISPASS	2008	DBLP DOI BibTeX RDF
2	Pu Liu, Sheldon X.-D. Tan, Wei Wu, Murli Tirumala	FEKIS: a fast architecture-level thermal analyzer for online thermal regulation.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	architecture, model reduction, thermal simulation
2	Duo Li, Sheldon X.-D. Tan, Murli Tirumala	Architecture-level thermal behavioral characterization for multi-core microprocessors.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Chunhua Yang, Jiancheng Wan	An Approach to Separating Security Concerns in E-Commerce Systems at the Architecture Level.	ISECS	2008	DBLP DOI BibTeX RDF	Security, E-commerce, Separation of concerns, Aspect oriented software development
2	Jeonghee Shin, Victor V. Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose	A Framework for Architecture-Level Lifetime Reliability Modeling.	DSN	2007	DBLP DOI BibTeX RDF
2	Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers	Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions.	DSN	2007	DBLP DOI BibTeX RDF
2	Mingliang Wei, Changhao Jiang, Marc Snir	Programming Patterns for Architecture-Level Software Optimizations on Frequent Pattern Mining.	ICDE	2007	DBLP DOI BibTeX RDF
2	Henry Muccini	Using Model Differencing for Architecture-level Regression Testing.	EUROMICRO-SEAA	2007	DBLP DOI BibTeX RDF
2	Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson	Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration.	ISQED	2006	DBLP DOI BibTeX RDF
2	Jinwen Xi, Peixin Zhong	A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	network-on-chip, SystemC, energy model
2	Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers	SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors.	DSN	2005	DBLP DOI BibTeX RDF
2	Jason Cong, Yiping Fan, Zhiru Zhang	Architecture-level synthesis for automatic interconnect pipelining.	DAC	2004	DBLP DOI BibTeX RDF	interconnect pipelining, multi-cycle communication, scheduling, high-level synthesis, register binding
2	Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Architecture-Level Performance Estimation for IP-Based Embedded Systems.	DATE	2004	DBLP DOI BibTeX RDF
2	John S. Seng, Dean M. Tullsen	Exploring the Potential of Architecture-Level Power Optimizations.	PACS	2003	DBLP DOI BibTeX RDF
2	Sherif M. Yacoub, Hany H. Ammar	A Methodology for Architecture-Level Reliability Risk Analysis.	IEEE Trans. Software Eng.	2002	DBLP DOI BibTeX RDF	Reliability risk analysis, component-dependency graphs, severity measures and dynamic metrics, software architecture, risk assessment, risk modeling
2	D. J. Soudris, M. M. Dasigenis, S. K. Vasilopoulou, Adonios Thanailakis	A CAD tool for architecture level exploration and automatic generation of RNS converters.	ISCAS	2001	DBLP DOI BibTeX RDF
2	Roberto Maro, Yu Bai, R. Iris Bahar	Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors.	PACS	2000	DBLP DOI BibTeX RDF	low-power, high-performance, architecture-level
1	Ming-yu Hsieh, Rolf Riesen, Kevin Thompson, William Song, Arun Rodrigues	SST: A Scalable Parallel Framework for Architecture-Level Performance, Power, Area and Thermal Simulation.	Comput. J.	2012	DBLP DOI BibTeX RDF
1	Mehdi Kamal, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram	An architecture-level approach for mitigating the impact of process variations on extensible processors.	DATE	2012	DBLP BibTeX RDF
1	Ke Chen, Sheng Li, Naveen Muralimanohar, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi	CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory.	DATE	2012	DBLP BibTeX RDF
1	Leslie Cheung, Ivo Krka, Leana Golubchik, Nenad Medvidovic	Architecture-level reliability prediction of concurrent systems.	ICPE	2012	DBLP DOI BibTeX RDF
1	Xiangyu Dong, Xiaoxia Wu, Yuan Xie, Yiran Chen, Hai Helen Li	Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation.	IET Computers & Digital Techniques	2011	DBLP DOI BibTeX RDF
1	Ming-yu Hsieh, Arun Rodrigues, Rolf Riesen, Kevin Thompson, William Song	A framework for architecture-level power, area, and thermal simulation and its application to network-on-chip design exploration.	SIGMETRICS Performance Evaluation Review	2011	DBLP DOI BibTeX RDF
1	Fabiana Jack Nogueira Santos, Flávia Maria Santoro, Claudia Cappelli	Crosscutting concerns at enterprise architecture level.	SMC	2011	DBLP DOI BibTeX RDF
1	Harry Sidiropoulos, Kostas Siozios, Dimitrios Soudris	A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAs.	FPL	2011	DBLP DOI BibTeX RDF
1	Harry Sidiropoulos, Kostas Siozios, Dimitrios Soudris	A Framework for Architecture-Level Exploration of 3-D FPGA Platforms.	PATMOS	2011	DBLP DOI BibTeX RDF
1	Fabian Brosig, Nikolaus Huber, Samuel Kounev	Automated extraction of architecture-level performance models of distributed component-based systems.	ASE	2011	DBLP DOI BibTeX RDF
1	Fabian Brosig	Online Performance Prediction with Architecture-Level Performance Models.	Software Engineering (Workshops)	2011	DBLP BibTeX RDF
1	Gang Huang 0001, Yihan Wu	Towards architecture-level middleware-enabled exception handling of component-based systems.	CBSE	2011	DBLP DOI BibTeX RDF
1	Sheng Li, Ke Chen, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi	CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala	Parameterized architecture-level dynamic thermal models for multicore microprocessors.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
1	Pablo Antonino, Slawomir Duszynski, Christian Jung, Manuel Rudolph	Indicator-based architecture-level security evaluation in a service-oriented environment.	ECSA Companion Volume	2010	DBLP DOI BibTeX RDF	security, service-oriented architecture, evaluation method, indicator, security evaluation
1	Mostafa E. Salehi, Hamed Dorosti, Sied Mehdi Fakhraie	Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network Applications.	DSD	2010	DBLP DOI BibTeX RDF
1	Harry Sidiropoulos, Kostas Siozios, Dimitrios Soudris	NAROUTO: An open-source framework for supporting architecture-level exploration at heterogeneous FPGAS.	ICECS	2010	DBLP DOI BibTeX RDF
1	Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun	Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers.	DAC	2010	DBLP DOI BibTeX RDF	optimization, design space exploration, SRAM, virtual prototype, iterative design
1	Diego Bernini	Architectural abstractions for space and time awareness: the case of responsive environments.	ECSA Companion Volume	2010	DBLP DOI BibTeX RDF	space-awareness, time-awareness, software architectures, publish-subscribe, responsive environments, architectural abstractions
1	Matthias Galster	Describing variability in service-oriented software product lines.	ECSA Companion Volume	2010	DBLP DOI BibTeX RDF	modeling, service-oriented architectures, variability
1	Omer Khan, Sandip Kundu	A model to exploit power-performance efficiency in superscalar processors via structure resizing.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	modeling, power
1	Himanshu Markandeya, Georgios Karakonstantis, Shriram Raghunathan, Pedro Irazoqui, Kaushik Roy	Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection.	ISLPED	2010	DBLP DOI BibTeX RDF	low power, epilepsy, biomedical, seizure detection
1	Byungwook Lee, Doheon Lee	Protein comparison at the domain architecture level.	BMC Bioinformatics	2009	DBLP DOI BibTeX RDF
1	Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala	Architecture-Level Thermal Characterization for Multicore Microprocessors.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Jude A. Rivers, Prabhakar Kudva	Reliability Challenges and System Performance at the Architecture Level.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Zafar Mehboob, Didar Zowghi	Industrial perspectives on architecture level change impact analysis in Web systems evolution.	WSE	2009	DBLP DOI BibTeX RDF
1	Xin Ge, Enjie Ding, Hongxia Xie	Promoting Data Mining Methodologies by Architecture-Level Optimizations.	WKDD	2009	DBLP DOI BibTeX RDF
1	Jianping Quan, Guoqiang Bai	A DPA-Resistant Digit-Parallel Modular Multiplier over GF (2m).	ITNG	2009	DBLP DOI BibTeX RDF	Modular multiplier, DPA-resistant, 1-bit masking, ECC, Architecture level
1	Christina Chavez, Alessandro F. Garcia, Thaís Vasconcelos Batista, Marcel Vinicius Medeiros Oliveira, Cláudio Sant'Anna, Awais Rashid	Composing architectural aspects based on style semantics.	AOSD	2009	DBLP DOI BibTeX RDF	architectural aspects, pointcut languages, style-based composition, architectural styles
1	David S. Kung, Ruchir Puri	CAD challenges for 3D ICs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo	Handling don't-care conditions in high-level synthesis and application for reducing initialized registers.	DAC	2009	DBLP DOI BibTeX RDF	RTL symbolic simulation, don't-care (DC), synthesis
1	Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers	Scalable high performance main memory system using phase-change memory technology.	ISCA	2009	DBLP DOI BibTeX RDF	dram caching, phase change memory, wear leveling
1	Joo-Young Kim, Seungjin Lee, Jinwook Oh, Minsu Kim, Hoi-Jun Yoo	A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management.	ISLPED	2009	DBLP DOI BibTeX RDF	energy efficient object recognition, multimedia processor, workload-aware dynamic power management
1	Wei Xu, Jibang Liu, Tong Zhang	Data manipulation techniques to reduce phase change memory write energy.	ISLPED	2009	DBLP DOI BibTeX RDF	low power, phase change memory
1	Yi Zhao, Jin Shi, Kai Zheng, Haichuan Wang, Haibo Lin, Ling Shao	Allocation wall: a limiting factor of Java applications on emerging multi-core platforms.	OOPSLA	2009	DBLP DOI BibTeX RDF	java, scalability, allocation
1	Ayse Kivilcim Coskun, Richard D. Strong, Dean M. Tullsen, Tajana Simunic Rosing	Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors.	SIGMETRICS/Performance	2009	DBLP DOI BibTeX RDF	reliability, chip multiprocessors, thermal management, simulation methodology
1	Iman I. Yusuf, Heinz W. Schmidt, Ian D. Peake	Evaluating recovery aware components for grid reliability.	ESEC/SIGSOFT FSE	2009	DBLP DOI BibTeX RDF	fault-tolerance, grid, components
1	Anand Singh, David J. Lilja	Improving risk assessment methodology: a statistical design of experiments approach.	SIN	2009	DBLP DOI BibTeX RDF	Plackett-Burman., control, risk assessment, design of experiments
1	Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin, James F. Buckwalter, Chung-Kuan Cheng	Prediction of high-performance on-chip global interconnection.	SLIP	2009	DBLP DOI BibTeX RDF	on-chip global interconnection, performance prediction, transmission line
1	Ralf Carbon, Sébastian Adam, Takayuki Uchida	Towards a product line approach for office devices: facilitating customization of office devices at Ricoh Co. Ltd.	SPLC	2009	DBLP DOI BibTeX RDF	flexibility, service orientation, product line engineering, product line architecture, application engineering
1	Vilas Sridharan, David R. Kaeli	Eliminating microarchitectural dependency from Architectural Vulnerability.	HPCA	2009	DBLP DOI BibTeX RDF
1	Xiaofeng Cui, Yanchun Sun, Sai Xiao, Hong Mei	Architecture Design for the Large-Scale Software-Intensive Systems: A Decision-Oriented Approach and the Experience.	ICECCS	2009	DBLP DOI BibTeX RDF
1	Min-Young Nam, Rodolfo Pellizzoni, Lui Sha, Richard M. Bradford	ASIIST: Application Specific I/O Integration Support Tool for Real-Time Bus Architecture Designs.	ICECCS	2009	DBLP DOI BibTeX RDF
1	Dionisio de Niz, Peter H. Feiler	Verification of Replication Architectures in AADL.	ICECCS	2009	DBLP DOI BibTeX RDF
1	Josep Torrellas	How to build a useful thousand-core manycore system?	IPDPS	2009	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty	Unified Challenges in Nano-CMOS High-Level Synthesis.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Kanwarpreet Sethi, Yuanfang Cai, Sunny Wong, Alessandro Garcia, Cláudio Sant'Anna	From retrospect to prospect: Assessing modularity and stability from software architecture.	WICSA/ECSA	2009	DBLP DOI BibTeX RDF
1	Wei Zhang 0002	Computing and Minimizing Cache Vulnerability to Transient Errors.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Eric Le Pors, Olivier Grisvard	Conceptual Modeling for System Requirements Enhancement.	Ada-Europe	2009	DBLP DOI BibTeX RDF	conceptual modeling, requirements, complex systems, System engineering
1	Mónica Pinto, Lidia Fuentes, Luis Fernández, Juan A. Valenzuela	Using AOSD and MDD to Enhance the Architectural Design Phase.	OTM Workshops	2009	DBLP DOI BibTeX RDF
1	Heiko Koziolek, Roland Weiss, Jens Doppelhamer	Evolving Industrial Software Architectures into a Software Product Line: A Case Study.	QoSA	2009	DBLP DOI BibTeX RDF
1	Eyad Alkassar, Mark A. Hillebrand, Dirk Leinenbach, Norbert Schirmer, Artem Starostin, Alexandra Tsyban	Balancing the Load.	J. Autom. Reasoning	2009	DBLP DOI BibTeX RDF	Pervasive formal verification, Software verification, Systems verification
1	Sheldon X.-D. Tan, Pu Liu, Lin Jiang, Wei Wu, Murli Tirumala	A Fast Architecture-Level Thermal Analysis Method for Runtime Thermal Regulation.	J. Low Power Electronics	2008	DBLP DOI BibTeX RDF
1	Kostas Siozios, Alexandros Bartzas, Dimitrios Soudris	Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology.	Int. J. Reconfig. Comp.	2008	DBLP DOI BibTeX RDF
1	Alex Shye, Berkin Özisikyilmaz, Arindam Mallik, Gokhan Memik, Peter A. Dinda, Robert P. Dick, Alok N. Choudhary	Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction.	ISCA	2008	DBLP DOI BibTeX RDF
1	Sima Emadi, Fereidoon Shams	An approach to non-functional requirements analysis at software architecture level.	CIT	2008	DBLP DOI BibTeX RDF
1	Diana Marculescu, Sani R. Nassif	Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level.	DATE	2008	DBLP DOI BibTeX RDF
1	Matt Nowak, Jose Corleto, Christopher Chun, Riko Radojcic	Holistic pathfinding: virtual wireless chip design for advanced technology and design exploration.	DAC	2008	DBLP DOI BibTeX RDF	design technology integration, design exploration, pathfinding
1	Jason Cong, Yi Zou	Lithographic aerial image simulation with FPGA-based hardwareacceleration.	FPGA	2008	DBLP DOI BibTeX RDF	co-processor acceleration, lithography simulation, FPGA
1	Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala	Parameterized transient thermal behavioral modeling for chip multiprocessors.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Leslie Cheung, Roshanak Roshandel, Nenad Medvidovic, Leana Golubchik	Early prediction of software component reliability.	ICSE	2008	DBLP DOI BibTeX RDF	modeling, software architecture, reliability prediction
1	Linda Dawson, Sea Ling, Maria Indrawan, Stephen Weeding, Juanita Fernando	Towards a framework for mobile information environments: a hospital-based example.	MoMM	2008	DBLP DOI BibTeX RDF	mobile information environment, context aware
1	Miroslav Knezevic, Kazuo Sakiyama, Yong Ki Lee, Ingrid Verbauwhede	On the high-throughput implementation of RIPEMD-160 hash algorithm.	ASAP	2008	DBLP DOI BibTeX RDF
1	Ryad Ben-El-Kezadri, Farouk Kamoun	A flexible channel access model for wireless network interface cards.	COMSWARE	2008	DBLP DOI BibTeX RDF
1	Ge Jun-wei, Tang Rong, Fang Yi-qiu	A MDA Based Aspect-Oriented Model Dynamic Weaving Framework.	CSSE	2008	DBLP DOI BibTeX RDF
1	Chunhan Wu, Xingyuan Zhang, Yuanyuan Wang	A Replay-Oriented Software Architecture for Easy Debugging.	CSSE	2008	DBLP DOI BibTeX RDF
1	Chunhua Yang, Haiyang Wang	A Process Algebra Based Aspect Weaving Model.	CSSE	2008	DBLP DOI BibTeX RDF
1	Zhenyu Liu, Satoshi Goto, Takeshi Ikenaga	Optimization of Propagate Partial SAD and SAD tree motion estimation hardwired engine for H.264.	ICCD	2008	DBLP DOI BibTeX RDF
1	Flávio Oquendo	Dynamic Software Architectures: Formally Modelling Structure and Behaviour with Pi-ADL.	ICSEA	2008	DBLP DOI BibTeX RDF
1	Junmin Ye, Wei Dong, Zhichang Qi	A Method to Generate Embedded Real-Time System Test Suites Based on Software Architecture Specifications.	ICYCS	2008	DBLP DOI BibTeX RDF
1	Jianfei Yin, Zhong Ming, Zhijiao Xiao, Hui Wang	A Web Performance Modeling Process Based on the Methodology of Learning from Data.	ICYCS	2008	DBLP DOI BibTeX RDF
1	Nikolai Joukov, Murthy V. Devarakonda, Kostas Magoutis, Norbert G. Vogl	Built-to-Order Service Engineering for Enterprise IT Discovery.	IEEE SCC	2008	DBLP DOI BibTeX RDF
1	Xinyi Dong, Michael W. Godfrey	Identifying Architectural Change Patterns in Object-Oriented Systems.	ICPC	2008	DBLP DOI BibTeX RDF
1	Wangyuan Zhang, Tao Li	Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology.	MICRO	2008	DBLP DOI BibTeX RDF
1	Bin Li, Li-Shiuan Peh, Priyadarsan Patra	Impact of Process and Temperature Variations on Network-on-Chip Design Exploration.	NOCS	2008	DBLP DOI BibTeX RDF
1	Jianjun Xu, Rui Shen, Qingping Tan	PRASE: An Approach for Program Reliability Analysis with Soft Errors.	PRDC	2008	DBLP DOI BibTeX RDF
1	Ambra Molesini, Alessandro F. Garcia, Christina von Flach G. Chavez, Thaís Vasconcelos Batista	On the Quantitative Analysis of Architecture Stability in Aspectual Decompositions.	WICSA	2008	DBLP DOI BibTeX RDF
1	Hui-Cheng Hsu, Kun-Bin Lee, Nelson Yen-Chung Chang, Tian-Sheuan Chang	Architecture Design of Shape-Adaptive Discrete Cosine Transform and Its Inverse for MPEG-4 Video Coding.	IEEE Trans. Circuits Syst. Video Techn.	2008	DBLP DOI BibTeX RDF