Search results for "arrays"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Cheng-Wen Wu, Peter R. Cappello	Easily Testable Iterative Logic Arrays.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	easily testable iterative logic arrays, octagonally connected arrays, combinational arrays, inhomogeneous arrays, bilateral arrays, test complexity, pipelined arrays, logic testing, systolic arrays, upper bound, matrix multiplication, cellular arrays, combinatorial circuits, multidimensional arrays
7	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis	Testing combinational iterative logic arrays for realistic faults.	VTS	1995	DBLP DOI BibTeX RDF	combinational iterative logic arrays, realistic faults, two-dimensional logic arrays, one-dimensional logic arrays, n-pattern tests, linear-testability, efficient test set, ILA, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, cellular arrays, logic arrays, C-testability, cell fault model
6	PeiZong Lee, Zvi M. Kedem	Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays.	IEEE Trans. Parallel Distrib. Syst.	1990	DBLP DOI BibTeX RDF	nested loop algorithms, multidimensional systolic arrays, correct transformation, programmable systolic arrays, general purpose programmable arrays, planar systolic array implementations, three-dimensional cube-graph algorithm, reindexed Warshall-Floyd path-finding algorithm, parallel algorithms, parallel processing, graph theory, matrix multiplication, data dependence, matrix algebra, cellular arrays, sufficient conditions, necessary conditions, algorithm transformations, automatic compilation
5	Wei-Kang Huang, Fabrizio Lombardi	An approach for testing programmable/configurable field programmable gate arrays.	VTS	1996	DBLP DOI BibTeX RDF	behavioral characterization, single fault detection, disjoint one-dimensional arrays, unilateral horizontal connections, common vertical input lines, array testing, logic blocks, field programmable gate arrays, field programmable gate arrays, VLSI, logic testing, integrated circuit testing, stuck-at fault, FPGA testing, functional fault, hybrid fault model
5	Graham M. Megson, Xian Chen	A synthesis method of LSGP partitioning for given-shape regular arrays. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	LSGP partitioning, given-shape regular arrays, computational polytope, activity matrix, timing vector, locally sequential globally parallel, parallel algorithms, data structures, systolic arrays, processor arrays
5	Michèle Dion, Tanguy Risset, Yves Robert	Resource-constrained scheduling of partitioned algorithms on processor arrays.	PDP	1995	DBLP DOI BibTeX RDF	physical processor arrays, communication capabilities, complex optimization problem, single integer linear programming problem, scheduling, computational complexity, complexity, linear programming, mapping, optimisation, processor arrays, partitioned algorithms, communication links, resource-constrained scheduling, optimal scheduling algorithms, linear processor arrays
5	Edwin Hsing-Mean Sha, Kenneth Steiglitz	Reconfigurability and Reliability of Systolic/Wavefront Arrays.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	wavefront arrays, fault-tolerant redundant structures, reliable arrays, application graph, finitely reconfigurable, locally reconfigurable, reliability, lower bound, fault tolerant computing, reconfigurability, time complexity, systolic arrays, systolic arrays, reconfigurable architectures, dynamic graphs, bounded-degree graphs
5	Viktor K. Prasanna, Yu-Chen Tsai	On Mapping Algorithms to Linear and Fault-Tolerant Systolic Arrays.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	fault-tolerant systolic arrays, linearly connected arrays, processor elements, VLSI model, Diogenes methodology, algorithms, fault tolerant computing, cellular arrays, propagation delay, matrix computations, mapping technique, linear systolic arrays
4	Alexander Thomasian, Gang Fu, Chunqi Han	Performance of Two-Disk Failure-Tolerant Disk Arrays.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Redundant arrays of independent disks, RAID5, RAID6, two-disk failure-tolerant arrays, EVENODD, RM2, operation in degraded mode, clustered RAID, fork-join requests, simulation, performance evaluation, queuing analysis, load imbalance, RDP
4	John P. McSorley	Double Arrays, Triple Arrays and Balanced Grids with v=r+c - 1.	Des. Codes Cryptography	2005	DBLP DOI BibTeX RDF	double arrays, triple arrays, balanced grids, designs, arrays
4	André DeHon	Design of programmable interconnect for sublithographic programmable logic arrays.	FPGA	2005	DBLP DOI BibTeX RDF	Manhattan mesh, sublithographic architecture, programmable logic arrays, nanowires, programmable interconnect
4	Sosina Martirosyan, Tran van Trung	On t-Covering Arrays.	Des. Codes Cryptography	2004	DBLP DOI BibTeX RDF	t-covering arrays, perfect hash families, orthogonal arrays, algebraic-geometric codes
4	André DeHon, Michael J. Wilson	Nanowire-based sublithographic programmable logic arrays.	FPGA	2004	DBLP DOI BibTeX RDF	sublithographic architecture, programmable logic arrays, nanowires
4	Martin C. Herbordt, Jade Cravy, Honghai Zhang, Calvin Lin, Hong Rao	An Array Control Unit for High Performance SIMD Arrays.	CAMP	2000	DBLP DOI BibTeX RDF	array control unit, high performance SIMD arrays, array utilization, SIMD arrays, parallel processing
4	T. Utsumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	Multiple-Valued Programmable Logic Arrays with Universal Literals. (PDF / PS)	ISMVL	1997	DBLP DOI BibTeX RDF	universal literals, multiple-valued programmable logic, universal literal generators, operator structures, programmable logic arrays, programmable logic arrays
4	Itsuo Takanami, Tadayoshi Horita	A built-in self-reconfigurable scheme for 3D mesh arrays.	ISPAN	1997	DBLP DOI BibTeX RDF	fault tolerant 3D processor arrays, 3D mesh arrays, self-reconfigurable scheme, track switches, fault compensation, reconfiguration, reconfigurable architectures
4	Bradly K. Fawcett, J. Watson	Reconfigurable Processing With Field Programmable Gate Arrays.	ASAP	1996	DBLP DOI BibTeX RDF	reconfigurable processing, internal architecture, computationally-intensive tasks, programmable solution, XC6200 FPGA architecture, SRAM control store, on-chip memory capability, field programmable gate arrays, interconnections, reconfigurable architectures, processors, coprocessors, coprocessors, SRAM chips, SRAM-based field programmable gate arrays
4	Guy Even, Ami Litman	Overcoming chip-to-chip delays and clock skews.	ASAP	1996	DBLP DOI BibTeX RDF	chip-to-chip delays, chip-to-chip interconnections, feasible clock period, large systolic linear arrays, systolic two-dimensional arrays, logic duplication, delays, logic design, systolic arrays, systolic array, functionality, retiming, clock skews
4	Seiken Yano	Unified scan design with scannable memory arrays.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	unified scan design, scannable memory arrays, single scan path, scan operation time, scannable register file, fault diagnosis, design for testability, design-for-testability, automatic testing, logic CAD, flip-flops, flip-flops, arrays, shift registers, integrated memory circuits
4	Timothy J. Schulz	Coherent array imaging with sparse arrays. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	antenna phased arrays, sparse arrays, coherent array imaging, phased-array imaging systems, Fourier inversion, coherent imaging system, image processing, maximum likelihood estimation, maximum-likelihood estimation, missing data, incomplete data, array signal processing, aperture
4	Anmol Mathur, K. C. Chen, C. L. Liu	Re-engineering of timing constrained placements for regular architectures.	ICCAD	1995	DBLP DOI BibTeX RDF	Xilinx 3000 FPGA architecture, engineering requirements, regular architectures, timing constrained placements reengineering, FPGAs, field programmable gate arrays, logic CAD, program debugging, systems re-engineering, logic arrays, design flow, gate arrays, design specification, timing performance, design cycle, design debugging
4	Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng	Automatic synthesis of gate-level timed circuits with choice.	ARVLSI	1995	DBLP DOI BibTeX RDF	gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates
4	John Schewel, Michael Thornburg, Steve Casselman	Transformable computers & hardware object technology. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	transformable computers, hardware object technology, reconfigurable aspects, computationally intensive software algorithms, on-the-fly use, field programmable gate arrays, field programmable gate arrays, programming, reconfigurable architectures, programmable logic arrays, hardware design, performance gain
4	David Naylor, Simon Jones	A Performance Model for Multilayer Neural Networks in Linear Arrays.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	throughput rate, input-output bandwidth, two-hidden-layer network, performance evaluation, performance, performance model, latency, systolic arrays, multilayer perceptrons, feedforward neural nets, linear arrays, multilayer neural networks
4	John C. Ramirez, Rami G. Melhem	Computational Arrays with Flexible Redundancy.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	flexible redundancy, computational arrays, processor/switch array, redundant arrays, Markov chain techniques, probability arguments, fault tolerant arrays, defect avoidance, parallel processing, fault tolerant computing, reconfiguration, redundancy, redundancy, embedding, logic design, fault detection, correction, fault masking, faulty processors, reconfiguration algorithms
4	Massimo Maresca	Polymorphic Processor Arrays.	IEEE Trans. Parallel Distrib. Syst.	1993	DBLP DOI BibTeX RDF	polymorphic processor arrays, mesh-connected arrays, PPA, low complexity algorithms, PPA programming model, computational complexity, parallel processing, parallel computers, parallel architectures, multiprocessor interconnection networks
4	Sy-Yen Kuo, Sheng-Chiech Liang	Concurrent Error Detection and Correction in Real-Time Systolic Sorting Arrays.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	online error correction, two level pipelining, real-time systolic sorting arrays, online error detection, VLSI sorting arrays, functional errors, data errors, real-time systems, parallel algorithms, VLSI, sorting, error correction codes, systolic arrays, error detection codes, concurrent error detection, high-throughput, self-checking, WSI, concurrent error correction
4	H. V. Jagadish, Thomas Kailath	A Family of New Efficient Arrays for Matrix Multiplication.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	regular iterative algorithm, matrix multiplication arrays, iteration vector, conventional arrays, processor cells, iterative methods, matrix algebra, cellular arrays, multiplying circuits
3	Jennifer B. Sartor, Stephen M. Blackburn, Daniel Frampton, Martin Hirzel, Kathryn S. McKinley	Z-rays: divide arrays and conquer speed and flexibility.	PLDI	2010	DBLP DOI BibTeX RDF	arraylets, z-rays, compression, arrays, heap
3	Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain	Design space exploration of throughput-optimized arrays from recurrence abstractions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, dynamic programming, systolic array, throughput optimization, recurrences
3	Alejandro Castillo Atoche, Deni Torres Román, Yuriy Shkvarko	Near Real Time Enhancement of Remote Sensing Imagery Based on a Network of Systolic Arrays.	CIARP	2009	DBLP DOI BibTeX RDF	Network of Systolic Arrays, Remote Sensing, Hardware/Software Co-Design
3	Theodoros Kaifas, Katherine Siakavara, Dimitrios Babas, George Miaris, Elias Vafiadis, John N. Sahalos	On the Design of Direct Radiating Antenna Arrays with Reduced Number of Controls for Satellite Communications.	MOBILIGHT	2009	DBLP DOI BibTeX RDF	Array Synthesis, Direct Radiating Arrays (DRA), Fractal Antennas, Orthogonal Method (OM)
3	Josue Bracho-Rios, Jose Torres-Jimenez, Eduardo Rodriguez-Tello	A New Backtracking Algorithm for Constructing Binary Covering Arrays of Variable Strength.	MICAI	2009	DBLP DOI BibTeX RDF	Software testing, Branch and Bound, Covering Arrays
3	Yee Jern Chong, Sri Parameswaran	Flexible multi-mode embedded floating-point unit for field programmable gate arrays.	FPGA	2009	DBLP DOI BibTeX RDF	dual-precision, embedded block, fpu, fpga, floating-point, fpga architecture
3	David B. Thomas, Lee W. Howes, Wayne Luk	A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation.	FPGA	2009	DBLP DOI BibTeX RDF	mppa, fpga, monte-carlo, random numbers, gpu
3	Timothy de Vries, Hui Ke, Sanjay Chawla, Peter Christen	Robust record linkage blocking using suffix arrays.	CIKM	2009	DBLP DOI BibTeX RDF	blocking, suffix arrays, record linkage
3	Qiang Wang, Subodh Gupta, Jason Helge Anderson	Clock power reduction for virtex-5 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
3	Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang	A comparison of via-programmable gate array logic cell circuits.	FPGA	2009	DBLP DOI BibTeX RDF	logic cell, via-programmable gate arrays
3	Shinya Kubota, Minoru Watanabe	A nine-context programmable optically reconfigurable gate array with semiconductor lasers.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	holographic memory, optically reconfigurable gate arrays, field programmable gate arrays
3	Dong Kyue Kim, Minhwan Kim, Heejin Park	Linearized Suffix Tree: an Efficient Index Data Structure with the Capabilities of Suffix Trees and Suffix Arrays.	Algorithmica	2008	DBLP DOI BibTeX RDF	Index data structures, Suffix trees, Suffix arrays, String algorithms
3	Lin Wan, Wenjiang J. Fu, Minghua Deng, Minping Qian	A Method to Correct Systematic Bias in Affymetrix SNP Arrays.	BMEI	2008	DBLP DOI BibTeX RDF	Affymetrix SNP arrays, copy number estimation, systematic bias
3	Nicolas Halbwachs, Mathias Péron	Discovering properties about arrays in simple programs.	PLDI	2008	DBLP DOI BibTeX RDF	sentinel, invariant synthesis, abstract interpretation, program verification, arrays, sorting algorithms
3	Jeremy Kepner	Multicore programming in pMatlab using distributed arrays.	CLADE	2008	DBLP DOI BibTeX RDF	parallel computing, distributed arrays
3	Michael Eagle, Tiffany Barnes	Wu's castle: teaching arrays and loops in a game.	ITiCSE	2008	DBLP DOI BibTeX RDF	CS1 education, Game2Learn, games, iteration, arrays
3	Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley	Efficient tiling patterns for reconfigurable gate arrays.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA hexagonal octagonal, tiling interconnect
3	José Aires, Gabriel Pereira Lopes, Joaquim Ferreira da Silva	Efficient multi-word expressions extractor using suffix arrays and related structures.	CIKM-iNEWS	2008	DBLP DOI BibTeX RDF	large corpus, multi-word expressions, extraction, suffix arrays, language independent
3	Morten Kromberg	Arrays of objects.	DLS	2007	DBLP DOI BibTeX RDF	multi-paradigm languages, object orientation, functional programming, language design, arrays
3	Ekow J. Otoo, Doron Rotem, Sridhar Seshadri	Optimal chunking of large multidimensional arrays for data warehousing.	DOLAP	2007	DBLP DOI BibTeX RDF	multi-dimensional arrays, data warehousing, chunking
3	Sandro Fouché, Myra B. Cohen, Adam A. Porter	Towards incremental adaptive covering arrays.	ESEC/SIGSOFT FSE (Companion)	2007	DBLP DOI BibTeX RDF	fault localization, covering arrays
3	Theo Mayer	The 4K format implications for visualization, VR, command & control and special venue application.	EDT	2007	DBLP DOI BibTeX RDF	1080, 2K, 4K, SXGA, SXRD, XGA, blended arrays, cube walls, edge blend, monitor arrays, projected arrays, special venue, video resolution, visualization, VR, video, command and control, HDTV
3	Cemal Yilmaz, Myra B. Cohen, Adam A. Porter	Covering Arrays for Efficient Fault Characterization in Complex Configuration Spaces.	IEEE Trans. Software Eng.	2006	DBLP DOI BibTeX RDF	fault characterization, Software testing, covering arrays, distributed continuous quality assurance
3	Marco Panduro, Carlos A. Brizuela, David Covarrubias, Claudio Lopez	A trade-off curve computation for linear antenna arrays using an evolutionary multi-objective approach.	Soft Comput.	2006	DBLP DOI BibTeX RDF	Non-regular arrays, Minor lobes, Radiation pattern, Genetic algorithms, Multi-objective
3	Javed Absar, Francky Catthoor	Reuse analysis of indirectly indexed arrays.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	indirectly indexed arrays, irregular access, reuse vector, data reuse, Scratch-pad
3	Song Fu, Cheng-Zhong Xu, Brian Wims, Ramzi Basharahil	Distributed shared arrays: A distributed virtual machine with mobility support for reconfiguration.	Cluster Computing	2006	DBLP DOI BibTeX RDF	Distributed shared arrays (DSA), Distributed virtual machine, DSA service migration, Parallel programming model
3	Giby Samson, Lawrence T. Clark	Circuit architecture for low-power race-free programmable logic arrays.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	circuit timing, low power, programmable logic arrays
3	Ming Wu, Xiao-Ming Dong, Huaiyang Li	Queue Network Modeling Approach to Analysis of the Optimal Stripe Unit Size for Disk Arrays under Synchronous I/O Workloads.	IWNAS	2006	DBLP DOI BibTeX RDF	stripe unit size, simulation, RAID, disk arrays, queue network model
3	Jean-Paul Calvi	Intertwining unisolvent arrays for multivariate Lagrange interpolation.	Adv. Comput. Math.	2005	DBLP DOI BibTeX RDF	unisolvent arrays, multivariate polynomials, Lagrange interpolation
3	Jeffrey W. Chastine, Jon A. Preston	Teaching 2D arrays using real-time video filters.	SIGITE Conference	2005	DBLP DOI BibTeX RDF	real-time, programming, filters, teaching, two-dimensional arrays
3	Mihai Udrescu, Lucian Prodan, Mircea Vladutiu	Improving quantum circuit dependability with reconfigurable quantum gate arrays.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	accuracy threshold, reconfigurable quantum gate arrays, coding
3	Avik Chakraborty	Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays.	VLSI Design	2005	DBLP DOI BibTeX RDF	Fault models, Testability, Design for test, Iterative logic arrays, Universal test sets, Reversible circuits
3	Dean S. Hoskins, Charles J. Colbourn, Douglas C. Montgomery	Software performance testing using covering arrays: efficient screening designs with categorical factors.	WOSP	2005	DBLP DOI BibTeX RDF	D-optimal designs, performance testing, covering arrays
3	Renée C. Bryce, Charles J. Colbourn	Test prioritization for pairwise interaction coverage.	A-MOST	2005	DBLP DOI BibTeX RDF	biased covering arrays, pairwise interaction coverage, greedy algorithm, covering arrays, software interaction testing, mixed-level covering arrays
3	Renée C. Bryce, Charles J. Colbourn	Constructing interaction test suites with greedy algorithms.	ASE	2005	DBLP DOI BibTeX RDF	biased covering arrays, t-way interaction coverage, greedy algorithm, covering arrays, software interaction testing, mixed-level covering arrays
3	Renée C. Bryce, Charles J. Colbourn	Test prioritization for pairwise interaction coverage.	ACM SIGSOFT Software Engineering Notes	2005	DBLP DOI BibTeX RDF	biased covering arrays, pairwise interaction coverage, greedy algorithm, covering arrays, software interaction testing, mixed-level covering arrays
3	Pantelis K. Varlamos, Panagiotis J. Papakanellos, Christos N. Capsalis	Design of Circular Switched Parasitic Dipole Arrays Using a Genetic Algorithm.	IJWIN	2004	DBLP DOI BibTeX RDF	Circular switched parasitic dipole arrays, electronic beam steering, induced EMF method, genetic algorithms, method of moments
3	Dean S. Hoskins, Renée Turban, Charles J. Colbourn	Experimental designs in software engineering: d-optimal designs and covering arrays.	WISER	2004	DBLP DOI BibTeX RDF	d-optimal designs, factorial experiments, covering arrays
3	Arifur Rahman, Vijay Polavarapuv	Evaluation of low-leakage design techniques for field programmable gate arrays.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, leakage power, multiplexer
3	Phil Ventura, Christopher A. Egert, Adrienne Decker	Ancestor worship in CS1: on the primacy of arrays.	OOPSLA Companion	2004	DBLP DOI BibTeX RDF	data structures, object-oriented programming, CS1, curriculum, object oriented-design, arrays, objects-first
3	Marc Levoy, Billy Chen, Vaibhav Vaish, Mark Horowitz, Ian McDowall, Mark T. Bolas	Synthetic aperture confocal imaging.	ACM Trans. Graph.	2004	DBLP DOI BibTeX RDF	camera arrays, coded aperture, confocal microscopy, projector arrays, shaped illumination, Light fields, synthetic aperture
3	Marcus Bednara, Jürgen Teich	Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms.	The Journal of Supercomputing	2003	DBLP DOI BibTeX RDF	regular processor arrays, FPGA, design automation, space-time mapping
3	Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky	Engineering a scalable placement heuristic for DNA probe arrays.	RECOMB	2003	DBLP DOI BibTeX RDF	DNA arrays, border minimization, probe placement
3	Peter Vanbroekhoven, Henk Corporaal, Francky Catthoor	Advanced copy propagation for arrays.	LCTES	2003	DBLP DOI BibTeX RDF	copy propagation, optimization, arrays, single assignment
3	Amit Chowdhary, John P. Hayes	General technology mapping for field-programmable gate arrays based on lookup tables.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	lookup tables (LUTs), multiple-LUT blocks, nonrooted trees, field-programmable gate arrays, mapping, synthesis, circuit partitioning, rooted trees, Basis
3	Josef Pieprzyk, Xian-Mo Zhang	Ideal Threshold Schemes from Orthogonal Arrays.	ICICS	2002	DBLP DOI BibTeX RDF	Orthogonal Arrays, Nonlinear Functions, Threshold Secret Sharing, Cheating Detection
3	Chris H. Q. Ding	An Optimal Index Reshuffle Algorithm for Multidimensional Arrays and Its Applications for Parallel Architectures.	IEEE Trans. Parallel Distrib. Syst.	2001	DBLP DOI BibTeX RDF	index reshuffle, vacancy tracking cycles, global exchange, dynamic remapping, multidimensional arrays
3	Tadayoshi Horita, Itsuo Takanami	Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	The 1$frac{1}{2}$-track switch model, reconfiguration, yield enhancement, wafer scale integration, mesh-connected processor arrays
3	Chor Ping Low	An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Degradable VLSI/WSI arrays, efficient heuristic, NP-completeness, greedy algorithm
3	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Sequential fault modeling, test pattern generation, robust testing, iterative logic arrays
3	Richard L. W. Brown	Interest made simple with arrays.	APL	2000	DBLP DOI BibTeX RDF	APL
3	Jürgen Bierbrauer, Holger Schellwat	Almost Independent and Weakly Biased Arrays: Efficient Constructions and Cryptologic Applications.	CRYPTO	2000	DBLP DOI BibTeX RDF	Low bias, almost independent arrays, Hermitian codes, Suzuki codes, Weil-Carlitz-Uchiyama bound, exponential sum method, Zyablov bound, authentication, Fourier transform, hashing, resiliency, Reed-Solomon codes
3	William L. Freking, Keshab K. Parhi	Performance-Scalable Array Architectures for Modular Multiplication.	ASAP	2000	DBLP DOI BibTeX RDF	high-radix algorithms, cylindrical arrays, folding transformation, systolic arrays, modular multiplication, scalable architectures
3	Ivana Mikic, Kohsia S. Huang, Mohan M. Trivedi	Activity Monitoring and Summarization for an Intelligent Meeting Room. (PDF / PS)	Workshop on Human Motion	2000	DBLP DOI BibTeX RDF	microphones, intelligent meeting room, multimodal sensor network, static cameras, interesting events, multi-person interactions, past-event reviews, active network control procedures, real-time system, summarization, active vision, cameras, arrays, intelligent environments, office automation, activity monitoring, microphone arrays, system specifications, integration framework, computerised monitoring, image processing equipment, office environment, active cameras
3	Behrooz Parhami, Ding-Ming Kwai	Data-Driven Control Scheme for Linear Arrays: Application to a Stable Insertion Sorter.	IEEE Trans. Parallel Distrib. Syst.	1999	DBLP DOI BibTeX RDF	stable sorting, tagged insertion sorter, VLSI, priority queue, distributed control, FIFO, linear processor arrays, Data-driven architectures
3	Tadayoshi Horita, Itsuo Takanami	Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions.	ISPAN	1999	DBLP DOI BibTeX RDF	The 1 1/2-track switch model, wefer scale integration, reconfiguration, yield enhancement, mesh-connected processor arrays
3	Patrick M. Lenders, Sanjay V. Rajopadhye	Multirate VLSI Arrays and Their Synthesis.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	Application specific processor arrays, index transformations, VLSI signal processing, systolic arrays, space-time mappings
3	Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Robust Sequential Fault Testing of Iterative Logic Arrays.	VTS	1997	DBLP DOI BibTeX RDF	Sequential Faults, Linear-testability, Fault Modeling, Automatic Test Generation, C-testability, Iterative Logic Arrays
3	Itsuo Takanami, Tadayoshi Horita	Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	self-reconstruction, digital neural circuits, Hopfield-type neural algorith, 1 1/2 -track switches, compensation paths, subcircuits, stable state, parallel state transitions, VLSI, mesh-connected processor arrays
3	Yoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi	CODA-R: a reconfigurable testbed for real-time parallel computation.	RTCSA	1997	DBLP DOI BibTeX RDF	CODA-R, reconfigurable testbed, real-time parallel computation, reconfigurable field programmable gate arrays, total execution time, prototype reconfigurable real-time parallel system, real-time parallel architecture, field programmable gate arrays, real-time system, processing elements, computing engine
3	Jarek Nieplocha, Robert J. Harrison	Shared Memory Programming in Metacomputing Environments: The Global Array Approach.	The Journal of Supercomputing	1997	DBLP DOI BibTeX RDF	NUMA memory architecture, Metacomputing, shared-memory programming, distributed arrays, global arrays
3	Kees van Reeuwijk, Will Denissen, Henk J. Sips, Edwin M. R. M. Paalvast	An Implementation Framework for HPF Distributed Arrays on Message-Passing Parallel Computer Systems.	IEEE Trans. Parallel Distrib. Syst.	1996	DBLP DOI BibTeX RDF	message aggregation, parallel computers, message passing, HPF, distributed arrays
3	Kumar N. Ganapathy, Benjamin W. Wah	Optimal Synthesis of Algorithm-Specific Lower-Dimensional Processor Arrays.	IEEE Trans. Parallel Distrib. Syst.	1996	DBLP DOI BibTeX RDF	polynomial-time search, transitive closure, processor arrays, optimal design, objective function, Design constraints, uniform recurrence equations
3	Sandy Pavel, Selim G. Akl	Efficient Algorithms for the Hough Transform on Arrays with Reconfigurable Optical Buses. (PDF / PS)	IPPS	1996	DBLP DOI BibTeX RDF	arrays with reconfigurable optical buses, Hough transform
3	Min-Young Lee, Myong-Soon Park	Double parity sparing for performance improvement in disk arrays. (PDF / PS)	ICPADS	1996	DBLP DOI BibTeX RDF	double parity sparing, parity data, performance evaluation, storage management, performance improvement, disk arrays, magnetic disc storage, degradation
3	Dirk Fimmel, Renate Merker	Propagation of I/O-Variables in Massively Parallel Processor Arrays.	PDP	1996	DBLP DOI BibTeX RDF	parallel processor arrays, systems of recurrence equations, automatic design methods, massive parallelism
3	Minesh I. Patel, N. Ranganathan	A VLSI System Architecture For Real-Time Intelligent Decision Making.	ASAP	1996	DBLP DOI BibTeX RDF	VLSI system architecture, real-time intelligent decision making, backpropagation based neural network, rule based fuzzy expert system, real-time decision, CMOS VLSI chip, real-time systems, VLSI, expert systems, systolic arrays, neural nets, backpropagation, CMOS integrated circuits, adaptive learning, linear systolic arrays
3	István Vassányi, István Erényi	Implementation of Processor Cells for Array Algorithms on FPGAs.	EUROMICRO	1996	DBLP DOI BibTeX RDF	array algorithms, processor cells, fine-grain array architectures, cellular image processing algorithms, placement-routing tool, field programmable gate arrays, FPGA, processor arrays
3	Mostafa H. Abd-El-Barr, M. N. Hasan	New MVL-PLA Structures Based on Current-Mode CMOS Technology. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic
3	William P. Marnane, W. R. Moore	Testing VLSI regular arrays.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	testing regular arrays, C-testability, test vector generation
3	Jai Menon	A Performance Comparison of RAID-5 and Log-Structured Arrays. (PDF / PS)	HPDC	1995	DBLP DOI BibTeX RDF	RAID-5, log-structured arrays, transaction-processing workloads, outboard disk controller, nonvolatile cache, physical disks, storage management, cache storage, performance comparison, compression ratio
3	H. Dhanesha, K. Falakshahi, Mark Horowitz	Array-of-arrays architecture for parallel floating point multiplication.	ARVLSI	1995	DBLP DOI BibTeX RDF	array-of-arrays architecture, parallel floating point multiplication, mantissa path, IEEE standard 754, dual-rail domino, HSpice simulation, capacitive load model, 53 bit, 10 ns, 4.3 V, 120 C, parallel architectures, trees, latency, floating point arithmetic, multiplying circuits, CMOS technology, Verilog, synergy, 1 micron