Search results for "asynchronous"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
7	Georgios K. Theodoropoulos, J. V. Woods	Simulating Asynchronous Architectures on Transputer Networks.	PDP	1996	DBLP DOI BibTeX RDF	asynchronous architecture simulation, asynchronous design techniques, clock related timing problems, CSP based parallel language, asynchronous architectural simulation models, parallel architectures, logic design, asynchronous circuits, circuit analysis computing, parallel languages, Occam, Occam, asynchronous logic, transputer systems, transputer networks
6	Rik van de Wiel	High-level test evaluation of asynchronous circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	high-level test evaluation, production fault tests, high-level circuit description, asynchronous 22 k transistor DCC error corrector IC, VLSI, logic testing, fault model, asynchronous circuits, asynchronous circuits, error detection codes
6	Chantal Ykman-Couvreur, Bill Lin	Optimised state assignment for asynchronous circuit synthesis.	ASYNC	1995	DBLP DOI BibTeX RDF	optimised state assignment, asynchronous circuit synthesis, complete state coding, state graph level, asynchronous benchmarks, circuit area, logic design, encoding, asynchronous circuits, computation time, state assignment
6	Jelio T. Yantchev, C. G. Huang, Mark B. Josephs, I. M. Nedelchev	Low-latency asynchronous FIFO buffers.	ASYNC	1995	DBLP DOI BibTeX RDF	buffer circuits, low-latency asynchronous FIFO buffers, parallel asynchronous implementation, interface circuitry, inter-chip communication wires, acknowledge signal, high-throughput multiple-burst signalling scheme, packet switching, asynchronous circuits, pipeline processing, propagation delay
6	C. Farnsworth, David A. Edwards, Jianwei Liu, S. S. Sikand	A hybrid asynchronous system design environment.	ASYNC	1995	DBLP DOI BibTeX RDF	hybrid asynchronous system design environment, hybrid design scheme, asynchronous circuit synthesis, Tangram silicon complier, synchronous design techniques, concurrency, high level synthesis, asynchronous circuits, power reduction, performance gains, micropipelines
6	Joep L. W. Kessels	VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player.	ASYNC	1995	DBLP DOI BibTeX RDF	digital audio tape, VLSI programming, low-power asynchronous Reed-Solomon decoder, DCC player, Tangram, minimal power dissipation, low-power cost-effective design, VLSI, logic programming, power consumption, power consumption, asynchronous circuits, asynchronous circuit, decoding, Reed-Solomon codes
5	Marc Renaudin, Pascal Vivet, Frédéric Robin	ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor.	ASYNC	1998	DBLP DOI BibTeX RDF	asynchronous microprocessor, quasi-delay-insensitive circuits, standard-cell asynchronous design
5	Sam S. Appleton, Shannon V. Morton, Michael J. Liebelt	A new method for asynchronous pipeline control.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF	asynchronous pipeline control, static logic control, dynamic logic control, flow controlled asynchronous method, asynchronous circuits, VLSI architecture
5	Karl M. Fant, Scott A. Brandt	NULL Convention Logic/sup TM/: A Complete And Consistent Logic For Asynchronous Digital Circuit Synthesis.	ASAP	1996	DBLP DOI BibTeX RDF	consistent logic, asynchronous digital circuit synthesis, symbolically complete logic, asynchronous digital circuits, asynchronous circuits, multivalued logic, three value logic, Boolean logic, NULL Convention Logic, four value logic
5	R. S. Hogg, W. I. Hughes, David W. Lloyd	A Novel Asynchronous ALU for Massively Parallel Architectures.	PDP	1996	DBLP DOI BibTeX RDF	novel asynchronous ALU, self timed asynchronous bit serial massively parallel architecture, fixed word length, small magnitude data, self timed communication techniques, self timed single instruction systolic array, ST-SISA, self timed delay insensitive techniques, parallel architectures, systolic arrays, asynchronous circuits, clock skew, massively parallel architectures, clocked control, arithmetic logic unit
5	Robert M. Fuhrer, Bill Lin, Steven M. Nowick	Algorithms for the optimal state assignment of asynchronous state machines.	ARVLSI	1995	DBLP DOI BibTeX RDF	optimal state assignment, asynchronous state machines, state codes, race-free state assignment, hazard-free state assignment, input encoding problem, sum-of-products implementations, finite state machines, asynchronous circuits, state assignment, minimisation of switching nets, hazards and race conditions, asynchronous sequential logic
5	O. A. Petlin, Stephen B. Furber	Scan testing of asynchronous sequential circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits
5	Alexandre Yakovlev, Victor Varshavsky, Vyacheslav Marakhovsky, Alexei L. Semenov	Designing an asynchronous pipeline token ring interface.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous pipeline token ring interface, speed-independent interface, reliable communication medium, on-board multicomputer, asynchronous buses, point-to-point interconnections, syntax-driven implementation, channel protocol controller, protocols, fairness, multiprocessor interconnection networks, local area networks, pipeline processing, deadlock-freedom, token networks
5	Eckhard Grass, S. Jones	Asynchronous circuits based on multiple localised current-sensing completion detection.	ASYNC	1995	DBLP DOI BibTeX RDF	dual rail coding, Current-Sensing Completion Detection, Current-Sensing Circuits, logic design, power consumption, asynchronous circuits, asynchronous circuits, granularity, parallel multiplier, BiCMOS
5	Shannon V. Morton, Sam S. Appleton, Michael J. Liebelt	ECSTAC: a fast asynchronous microprocessor.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous microprocessor, ECSTAC, two-phase communication, processor pipeline, register tagging, branch techniques, block simulation, caches, logic design, asynchronous circuits, microprocessor chips
5	David A. Kearney, Neil W. Bergmann	Performance evaluation of asynchronous logic pipelines with data dependent processing delays.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous logic pipelines, data dependent processing delays, logic stages, data dependent delay, two valued random variable, performance evaluation, performance evaluation, asynchronous circuits, pipeline processing, latches
5	C. J. Elston, D. B. Christianson, P. A. Findlay, G. B. Steven	Hades-towards the design of an asynchronous superscalar processor.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous superscalar processor, Hades, generic processor architecture, asynchronous processor design, decoupled operand forwarding, register writeback, computer architecture, logic design
5	Chia-Hsing Chien, Mark A. Franklin, Tienyo Pan, Prithvi Prabhu	ARAS: asynchronous RISC architecture simulator.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous RISC architecture simulator, ARAS, pipeline instruction simulator, benchmark programs, pipeline configuration, asynchronous pipeline architectures, performance evaluation, parallel architectures, virtual machines, performance measurements, pipeline processing
5	Chantal Ykman-Couvreur, Bill Lin	Efficient state assignment framework for asynchronous state graphs. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	state assignment framework, asynchronous state graphs, state graph level, complete state coding problem, circuit area, logic design, encoding, asynchronous circuits, asynchronous circuits, computation time, state assignment
4	Martin Simlastík, Viera Stopjaková	Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey.	PATMOS	2008	DBLP DOI BibTeX RDF	Asynchronous Digital Circuits, Self-time Digital Circuits, Synchronous-to-asynchronous Conversion, DLAP, De-synchronization, Phased Logic, LEDR, Low Power, Null Convention Logic, SADT
4	Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach	A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.	NOCS	2008	DBLP DOI BibTeX RDF	NoC testing, QDI asynchronous logic, Network-on-Chip, DfT, testability, NoC, Design-for-Test, GALS, SoC testing, testing methodology, on-chip communication, Globally Asynchronous - Locally Synchronous
4	Sufian Sudeng, Arthit Thongtak	Template Based: A Novel STG Based Logic Synthesis for Asynchronous Control Circuits.	World Congress on Engineering (Selected Papers)	2008	DBLP DOI BibTeX RDF	asynchronous control circuits, asynchronous DMA controller, template based technique, logic synthesis, Signal Transition Graph (STG)
4	Pietro Cicotti, Scott B. Baden	Short Paper: Asynchronous programming with Tarragon.	HPDC	2006	DBLP DOI BibTeX RDF	run time virtualized process structure, asynchronous programming, Tarragon run time library, actor-based programming model, latency tolerant asynchronous event driven simulation, meta data
4	Octavian Petre, Hans G. Kerkhoff	Scan Test Strategy for Asynchronous-Synchronous Interfaces.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	globally asynchronous locally synchronous (GALS), asynchronous synchronous interface, synchronizers, scan test
4	Jerry Zhigang Li, Sharon Elizabeth Bratt	Activity Theory as Tool for Analyzing Asynchronous Learning Networks (ALN).	ICWL	2004	DBLP DOI BibTeX RDF	online conference, E-learning, computer-mediated communication, Asynchronous communication, activity theory, instructional design, web-based learning, online discussion, Asynchronous Learning Networks
4	F. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin	Asynchronous FIR Filters: Towards a New Digital Processing Chain.	ASYNC	2004	DBLP DOI BibTeX RDF	Level-crossing sampling, FIR filter, Speech processing, Asynchronous design, Irregular sampling
4	Mathew A. Sacker, Andrew D. Brown, Peter R. Wilson, Andrew J. Rushton	A General Purpose Behavioural Asynchronous Synthesis System.	ASYNC	2004	DBLP DOI BibTeX RDF	Behavioural synthesis, asynchronous synthesis, cryptography
4	Christof Fetzer	Perfect Failure Detection in Timed Asynchronous Systems.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Perfect failure detection, timed asynchronous system model, asynchronous distributed systems, crash failures
4	Atanu Chattopadhyay, Zeljko Zilic	A globally asynchronous locally dynamic system for ASICs and SoCs.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	all-digital clock generation, dynamic clock manager, globally asynchronous locally synchronous system, asynchronous design
4	Alain Girault, Clément Ménier	Automatic Production of Globally Asynchronous Locally Synchronous Systems.	EMSOFT	2002	DBLP DOI BibTeX RDF	Globally synchronous-locally asynchronous (GALS), asynchronous communications, hardware/software codesign, distributed architectures, synchronous circuits, automatic distribution
4	Victor Varshavsky, Vyacheslav Marakhovsky	GALA Approach in Design of Asynchronous Control for Counterflow Pipeline Processor.	DELTA	2002	DBLP DOI BibTeX RDF	GALA - Globally Asynchronous Locally Arbitrary, Counterflow Pipeline Processor, Synchronous Prototype, Arbitration, Asynchronous Design
4	Amy Streich, Alex Kondratyev, Lief Sorensen	Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach.	ASYNC	2002	DBLP DOI BibTeX RDF	ATPG, asynchronous circuits, stuck-at faults, partial scan
4	Recep O. Ozdag, Peter A. Beerel	High-Speed QDI Asynchronous Pipelines.	ASYNC	2002	DBLP DOI BibTeX RDF	conditional split, conditional join, QDI, pipelines, asynchronous, dynamic logic, joins, non-linear, fine-grain, micropipelines, forks
4	José A. Tierno, Sergey Rylov, Alexander Rylyakov, Montek Singh, Steven M. Nowick	An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz.	ASYNC	2002	DBLP DOI BibTeX RDF	PRML read channel, magnetic recording, asynchronous pipeline, digital arithmetic, FIR filter, dynamic logic, high-throughput, low-latency, distributed arithmetic, mixed timing
4	Frank te Beest, Kees van Berkel, Ad M. G. Peeters	Adding Synchronous and LSSD Modes to Asynchronous Circuits.	ASYNC	2002	DBLP DOI BibTeX RDF	design for testability, asynchronous circuits, scan test, LSSD
4	Eckhard Grass, Bodhisatya Sarker, Koushik Maharatna	A Dual-Mode Synchronous/Asynchronous CORDIC Processor.	ASYNC	2002	DBLP DOI BibTeX RDF	CORDIC processor, dual-mode, synchronous, asynchronous, self-timed
4	Donna Dufner, Ojoung Kwon, William Rogers	Enriching Asynchronous Learning Networks through the Provision of Virtual Collaborative Learning Spaces: A Research Pilot. (PDF / PS)	HICSS	2001	DBLP DOI BibTeX RDF	Virtual Workgroup Environment, Web-enabled GDSS, Cooperative Document Production, Asynchronous Mode of Communication, Collaborative Learning, Distance Learning, Online Learning, Cooperative Learning, Collaboratories, Asynchronous Learning Networks
4	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic.	PRDC	2000	DBLP DOI BibTeX RDF	dual-rail differential logic, multiple-valued current-mode circuits, asynchronous-control circuit, logic testing, asynchronous circuits, self-checking circuit, current-mode logic, current-mode circuits
4	Michael J. Liebelt, Cheng-Chew Lim	A method for determining whether asynchronous circuits are self-checking.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise
4	Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy	Fsimac: a fault simulator for asynchronous sequential circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	Fsimac, gate-level fault simulator, Muller C-elements, complex domino gates, high-speed design, min-max timing analysis, min-max rime stamps, CA-BIST, waveform model, logic testing, built-in self test, timing, cellular automata, Cellular Automata, sequential circuits, iterative methods, fault simulation, fault simulator, asynchronous circuits, stuck-at faults, iterations, delay faults, combinational logic, feedback loops, pseudo-random tests, gate-delay faults, asynchronous sequential circuits
4	Tswen-Yuh Hsiao, Win-Tsung Lo, Shyan-Ming Yuan	An Asynchronous Message Exchange System on CORBA.	TOOLS	2000	DBLP DOI BibTeX RDF	asynchronous message exchange system, Internet-scale event-driven data exchange architecture, asynchronous publish/subscriber communication model, Inprise Visibroker, Java product families, distributed loosely-coupled, heterogeneous network systems, event generation, event observation, Java, Internet, CORBA, legacy systems, electronic data interchange, distributed object management, event service, OMG, naming services, naming service, event notification, Java programming language
4	Tiberiu Chelcea, Steven M. Nowick	Low-Latency Asynchronous FIFO's Using Token Rings.	ASYNC	2000	DBLP DOI BibTeX RDF	VLSI, asynchronous, FIFO, low-latency, digital design, token ring
4	Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken	DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits.	ASYNC	2000	DBLP DOI BibTeX RDF	DUDES, testing, ATPG, fault model, asynchronous circuit, stuck-at fault, fault collapsing
4	Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri	CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder.	ASYNC	2000	DBLP DOI BibTeX RDF	pulse logic, switch-level fault simulation, Cellular Automata, BIST, asynchronous circuits, testability, stuck-at faults, domino logic, self-timed circuits, dynamic circuits
4	Montek Singh, Steven M. Nowick	High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths.	ASYNC	2000	DBLP DOI BibTeX RDF	fine-grain pipelining, VLSI, pipelines, asynchronous, dynamic logic, FIFO, high-throughput, digital design
4	Joep L. W. Kessels, Gerrit den Besten, Ad M. G. Peeters, Torsten Kramer, Volker Timm	Applying Asynchronous Circuits in Contactless Smart Cards.	ASYNC	2000	DBLP DOI BibTeX RDF	low-power asynchronous circuits, contactless devices, DES cryptography, smart cards
4	François Verdier, Alain Mérigot, Bertrand Zavidovique	Fast Stable Matching Algorithm using Asynchronous Parallel Programming Model.	CAMP	2000	DBLP DOI BibTeX RDF	fast stable matching algorithm, asynchronous parallel programming model, stable marriage algorithm, massively parallel asynchronous model, asynchronously communicating processors, image processing problem, image processing, 3D reconstruction, image matching, database search
4	Martin Benes, Steven M. Nowick, Andrew Wolfe	A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors.	ASYNC	1998	DBLP DOI BibTeX RDF	Huffman encoding, embedded systems, asynchronous, embedded processors, dynamic logic, hazards, digital design
4	Bruce W. Hunt, Kenneth S. Stevens, Bruce W. Suter, Donald S. Gelosh	A Single Chip Low Power Asynchronous Implementation of an FFT Algorithm for Space Applications.	ASYNC	1998	DBLP DOI BibTeX RDF	Radiation Tolerant, VLSI, FFT, Asynchronous
4	Aiguo Xie, Peter A. Beerel	Accelerating Markovian Analysis of Asynchronous Systems using String- based State Compression.	ASYNC	1998	DBLP DOI BibTeX RDF	stationary analysis, state compression, performance evaluation, Asynchronous systems, power estimation, convergence rate, Markov chain models, feedback vertex set
4	W. J. Bainbridge, Stephen B. Furber	Asynchronous Macrocell Interconnect using MARBLE.	ASYNC	1998	DBLP DOI BibTeX RDF	Macrocell Bus, VLSI, Interconnect, Asynchronous
4	D. J. Kinniment, Alexandre Yakovlev, Fei Xia, B. Gao	Towards Asynchronous A-D Conversion.	ASYNC	1998	DBLP DOI BibTeX RDF	analogue to digital conversion, synchronisers, asynchronous circuits, arbitration, signal transition graphs, metastability
4	Ross Smith, Karl Fant, Dave Parker, Rick Stephani, Ching-Yi Wang	An Asynchronous 2-D Discrete Cosine Transform Chip.	ASYNC	1998	DBLP DOI BibTeX RDF	DCT, asynchronous, threshold logic, bit-serial
4	Kåre T. Christensen, Peter Jensen, Peter Korger, Jens Sparsø	The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core. (PDF / PS)	ASYNC	1998	DBLP DOI BibTeX RDF	Asynchronous circuits and systems, low-power, microprocessor design
4	Hans van Gageldonk, Kees van Berkel, Ad M. G. Peeters, Daniel Baumann, Daniel Gloor, Gerhard Stegmann	An Asynchronous Low-Power 80C51 Microcontroller.	ASYNC	1998	DBLP DOI BibTeX RDF	VLSI-programming, low-power, microcontrollers, asynchronous design
4	Allen E. Sjogren, Chris J. Myers	Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline.	ARVLSI	1997	DBLP DOI BibTeX RDF	Mixed synchronous/asynchronous interfacing, stoppable clocks, high-speed pipelines, globally synchronous locally asynchronous, metastability, synchronization failure
4	David A. Kearney, Neil W. Bergmann	Bundled Data Asynchronous Multipliers with Data Dependent Computation Times.	ASYNC	1997	DBLP DOI BibTeX RDF	asynchronous logic data dependent performance multiplier
4	Kenneth Y. Yun, Ayoob E. Dooply, Julio Arceo, Peter A. Beerel, Vida Vakilotojar	The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver.	ASYNC	1997	DBLP DOI BibTeX RDF	Differential equation solver, Low control, Completion sensing, Model checking, Distributed control, overhead, Asynchronous design
4	D. A. Gilbert, Jim D. Garside	A Result Forwarding Mechanism for Asynchronous Pipelined Systems.	ASYNC	1997	DBLP DOI BibTeX RDF	dependency, asynchronous, Exception, reorder buffer
4	Sam S. Appleton, Shannon V. Morton, Michael J. Liebelt	Two-Phase Asynchronous Pipeline Control.	ASYNC	1997	DBLP DOI BibTeX RDF	two-phase asynchronous pipeline control, bounded-delay model, prototype microprocessor, microprocessor chips
4	Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, P. Day, N. C. Paver	AMULET2e: An Asynchronous Embedded Controller.	ASYNC	1997	DBLP DOI BibTeX RDF	Low power, Microprocessors, Asynchronous design, Embedded control
4	Pedro A. Molina, Peter Y. K. Cheung	A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems.	ASYNC	1997	DBLP DOI BibTeX RDF	Tri-state Buffers, Asynchronous, Composability, Bus, Data Path, Delay-Insensitive, Handshake Circuits
4	Steven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel	Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders.	ASYNC	1997	DBLP DOI BibTeX RDF	completion detection, Brent-Kung, Carry-Bypass, asynchronous, adders, hazards, high-performance design
4	Joep L. W. Kessels, Paul Marston	Designing Asynchronous Standby Circuits for a Low-Power Pager. (PDF / PS)	ASYNC	1997	DBLP DOI BibTeX RDF	pager, loadable counter, synchronous/asynchronous, low-power, co-design
4	Nikolaos Gaitanis, Dimitris Gizopoulos, Antonis M. Paschalis, Panagiotis Kostarakis	An asynchronous totally self-checking two-rail code error indicator.	VTS	1996	DBLP DOI BibTeX RDF	asynchronous TSC error indicator, totally self-checking error indicator, concurrent detection, two-rail code error indicator, CMOS implementation, VLSI, logic testing, delays, integrated circuit testing, error detection, automatic testing, asynchronous circuits, CMOS logic circuits, delay faults
4	Jan Hlavicka, Stanislav Racek, Pavel Smrha	Functional Validation of Fault-Tolerant Asynchronous Algorithms.	EUROMICRO	1996	DBLP DOI BibTeX RDF	fault-tolerant asynchronous algorithms, distributed asynchronous algorithms, algorithm correctness, process-oriented discrete simulation, fault injector, C-based validation tool, C-Sim, C-coded implementation, distributed election algorithm, formal specification, communication channels, time behavior, functional validation, state observer, failure semantics
4	Guillermo A. Alvarez, Marcelo O. Fernández, Ragelio A. Alvez, Sylvia Rodriguez, Julio A. Sánchez Avalos, Jorge L. C. Sanz	Run-time support for asynchronous parallel computations. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	asynchronous parallel computations, DREAM, asynchronous multiprocessors, global distributed arrays, dynamic communication patterns, performance evaluation, scalability, parallel computations, programming environments, multiprocessing systems, network latency, run-time support, performance results, distributed programming environment
4	Rosalie J. Ocker, Starr Roxanne Hiltz, Murray Turoff, Jerry Fjermestad	Computer support for distributed asynchronous software design teams: experimental results on creativity and quality.	HICSS	1995	DBLP DOI BibTeX RDF	distributed asynchronous software design teams, distributed asynchronous computer conferencing, automated post office, course assignment, formal specification, groupware, creativity, quality, systems analysis, software design, computer science, software development management, teleconferencing, software specifications, business, group interaction, graduate students, face-to-face meetings
4	Ding Lu, Carol Q. Tong	High level fault modeling of asynchronous circuits.	VTS	1995	DBLP DOI BibTeX RDF	high level fault modeling, transitional fault models, stuck-at-false model, stuck-at-true model, fault diagnosis, logic testing, timing, asynchronous circuits, asynchronous circuits, signal transition graph, signal flow graphs, self-timed circuits
4	Sridhar Narayanan, Melvin A. Breuer	Asynchronous multiple scan chain.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous multiple scan chains, scan flip-flops, control complexity, I/O pin count, DFT method, logic IC, logic testing, integrated circuit testing, design for testability, logic design, asynchronous circuits, flip-flops, integrated logic circuits, scan designs, boundary scan testing, test application time
4	Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng	Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.	VLSI Design	1995	DBLP DOI BibTeX RDF	stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions
4	Kenneth Y. Yun, David L. Dill	A high-performance asynchronous SCSI controller. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	peripheral interfaces, high-performance asynchronous SCSI controller, small computer systems interface, asynchronous pipeline, extended burst-mode machines, CMOS standard cell, data transfer throughput, distributed control scheme, extended burst-mode state machines, synchronisation, distributed control, CMOS integrated circuits, FIFO
4	Bret Stott, Dave Johnson, Venkatesh Akella	Asynchronous 2-D discrete cosine transform core processor. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	asynchronous 2-D discrete cosine transform core processor, self-timed design, CCITT compatible asynchronous DCT/IDCT processor, two-phase transition signaling, bounded delay approach, Sutherland's micropipeline, custom techniques, 2 /spl mu/ SCMOS technology, delays, discrete cosine transforms, digital signal processing chips, CMOS digital integrated circuits, standard cell, 2 micron
4	Ad M. G. Peeters, Kees van Berkel	Single-rail handshake circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	single-rail handshake circuits, four-phase handshake protocol, standard-cell library, technology migration, low-power applications, VLSI, protocols, energy-efficient, asynchronous circuits, asynchronous circuits, integrated logic circuits, cellular arrays
4	Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia, Angel Barriga Barros, Raúl Jiménez, José L. Huertas	New CMOS VLSI linear self-timed architectures.	ASYNC	1995	DBLP DOI BibTeX RDF	semiconductor storage, CMOS VLSI linear self-timed architectures, digital signal processor circuits, self-timed techniques, synchronous VLSI circuits, FIFO memories, VLSI, asynchronous circuits, asynchronous circuits, digital signal processing chips, CMOS memory circuits, hardware resources
4	Kees van Berkel, Ronan Burgess, Joep L. W. Kessels, Ad M. G. Peeters, Marly Roncken, Frits D. Schalij, Rik van de Wiel	A single-rail re-implementation of a DCC error detector using a generic standard-cell library.	ASYNC	1995	DBLP DOI BibTeX RDF	digital audio tape, DCC error detector, generic standard-cell library, single-rail re-implementation, fully asynchronous implementation, handshake signaling, single-rail data encoding, generic cell library, high-level Tangram description, intermediate architecture, high level synthesis, asynchronous circuits, error detection codes, integrated logic circuits, cellular arrays, power dissipation, handshake circuits
4	Chris J. Myers, Peter A. Beerel, Teresa H. Y. Meng	Technology mapping of timed circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	gate library, C-elements, ATACS, timing, logic design, logic CAD, asynchronous circuits, asynchronous circuits, timing information, AND gates, synthesis tool, OR gates, timed circuits
4	Kees van Berkel, Ferry Huberts, Ad M. G. Peeters	Stretching quasi delay insensitivity by means of extended isochronic forks.	ASYNC	1995	DBLP DOI BibTeX RDF	extended isochronic forks, isochronic-fork assumption, double-rail data paths, DCC error decoder, logic design, asynchronous circuits, asynchronous circuits, arbiter, delay insensitivity, handshake circuits
4	C. Rominger, Jean Claude Geffroy	Hazard analysis of structured sequential systems.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	structured sequential systems, time uncertainties, asynchronous sequential systems, nondeterministic phenomena, simulation method, structured systems, fault diagnosis, CAD, logic testing, timing, sequential circuits, logic CAD, asynchronous circuits, digital simulation, time analysis, circuit analysis computing, hazard analysis, asynchronous sequential logic
4	Garth Baulch, David Hemmendinger, Cherrice Traver	Analyzing and verifying locally clocked circuits with the concurrency workbench.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	locally clocked circuits, concurrency workbench, synchronous computational elements, concurrent system modelling, CCS process algebra, formal verification, timing, logic design, process algebra, logic CAD, asynchronous circuits, asynchronous circuits, circuit analysis computing, asynchronous communication
4	Seokjin Kim, Ramalingam Sridhar	A local clocking approach for self-timed datapath designs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	self-timed datapath designs, local clock control circuit, synchronous datapaths, asynchronous environment, locally-clocked multiplier, asynchronous system implementation, timing, logic design, logic design, digital arithmetic, asynchronous circuits, multiplying circuits
4	Michel Cosnard, Pierre Fraigniaud	Analysis of Asynchronous Polynomial Root Finding Methods on a Distributed Memory Multicomputer.	IEEE Trans. Parallel Distrib. Syst.	1994	DBLP DOI BibTeX RDF	poles and zeros, distributed memorysystems, asynchronous polynomial root finding, iterative polynomial root finding, locally convergent, asynchronous methods, synchronous, convergence, polynomials, convergence of numerical methods, distributed memory multicomputer, hypercube multicomputer, polynomial zeros
4	Venkatesh Akella, Ganesh Gopalakrishnan	Specification and Validation of Control-Intensive IC's in hopCP.	IEEE Trans. Software Eng.	1994	DBLP DOI BibTeX RDF	control-intensive integrated circuits, hopCP, asynchronous operations, multiple concurrent threads, Intel 8251, Universal Synchronous/Asynchronous Receiver/Transmitter, USART, synchronous message passing, distributed shared variables, asynchronous ports, compiled-code concurrent functional simulator, CFSIM, formal specification, formal methods, formal verification, specification, validation, message passing, specification languages, interrupt, digital simulation, hardware description language, microprocessor chips, hardware design, polling, computational requirements, synchronous operations
4	Anthony J. McAuley	Four State Asynchronous Architectures.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	four state asynchronous architectures, asynchronous wavefront array, one-dimensional multipliers, two-dimensional sorter, reliability, throughput, sequential circuits, many-valued logics, design complexity, asynchronous sequential logic
4	Weiguo Wang	An Asynchronous Two-Dimensional Self-Correcting Cellular Automaton	FOCS	1991	DBLP DOI BibTeX RDF	fault-free global synchronization clock, asynchronous two-dimensional self-correcting cellular automaton, arbitrary size, homogeneous asynchronous array, asynchronous environment, reliability, probability, reliable computation
4	Leonard R. Marino	The Effect of Asynchronous Inputs on Sequential Network Reliability.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Asynchronous arbiter, asynchronous sequential networks, flip-flop oscillations, inertial delay, input synchronization, metastable state, Schmitt trigger, synchronous sequential networks, reliability, asynchronous interactions
3	Peter A. Beerel, Georgios D. Dimou, Andrew Lines	Proteus: An ASIC Flow for GHz Asynchronous Designs.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF	slack matching, asynchronous place and route, high performance, design and test, communicating sequential processes, asynchronous design
3	Mahasweta Sarkar, Jeemil Shah	A asynchronous MAC layer channel selection scheme for multichannel ad hoc networks.	IWCMC	2010	DBLP DOI BibTeX RDF	channel selection scheme, single transceiver, ad-hoc networks, asynchronous, multi-channel
3	Neil Gershenfeld, David Dalrymple, Kailiang Chen, Ara Knaian, Forrest Green, Erik D. Demaine, Scott Greenwald, Peter Schmidt-Nielsen	Reconfigurable asynchronous logic automata: (RALA).	POPL	2010	DBLP DOI BibTeX RDF	reconfigurable, logic, asynchronous, automata
3	Zuzana Beerliová-Trubíniová, Martin Hirt, Jesper Buus Nielsen	On the theoretical gap between synchronous and asynchronous MPC protocols.	PODC	2010	DBLP DOI BibTeX RDF	cryptography, multi-party computation, asynchronous network, mpc
3	Arpita Patra, C. Pandu Rangan	Brief announcement: communication efficient asynchronous byzantine agreement.	PODC	2010	DBLP DOI BibTeX RDF	asynchronous, information theoretic security
3	Robert P. Biuk-Aghai, Keng Hong Lei	Chatting in the Wiki: synchronous-asynchronous integration.	Int. Sym. Wikis	2010	DBLP DOI BibTeX RDF	communication, synchronous, wiki, instant messaging, asynchronous
3	Aparna Chandramowlishwaran, Kathleen Knobe, Richard W. Vuduc	Applying the concurrent collections programming model to asynchronous parallel dense linear algebra.	PPOPP	2010	DBLP DOI BibTeX RDF	concurrent collections, asynchronous algorithms, dense linear algebra
3	Lixia Liu, Zhiyuan Li	Improving parallelism and locality with asynchronous algorithms.	PPOPP	2010	DBLP DOI BibTeX RDF	parallel numerical programs, data locality, memory performance, loop tiling, asynchronous algorithms
3	Hyukmin Son, Sanghoon Lee 0001	Multi-cell communications for OFDM-based asynchronous networks over multi-cell environments.	Wireless Networks	2009	DBLP DOI BibTeX RDF	Site selection diversity, Guard carrier, Network synchronization, Synchronization, OFDM, Multiple access interference, Asynchronous network
3	Rajat Subhra Chakraborty, Swarup Bhunia	A study of asynchronous design methodology for robust CMOS-nano hybrid system design.	JETC	2009	DBLP DOI BibTeX RDF	CMOS-nano co-design, dual-rail circuits, logic degradation, nano-scale crossbar, Asynchronous design, robust design, micropipelines
3	Jonathan S. Turner	Strong performance guarantees for asynchronous buffered crossbar scheduler.	IEEE/ACM Trans. Netw.	2009	DBLP DOI BibTeX RDF	asynchronous crossbars, crossbar schedulers, routers, switches, performance guarantees
3	Alexey Lopich, Piotr Dudek	Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Binary skeletonization, Grassfire transformation, Wave propagations, Asynchronous processing
3	Andy Jinqing Yu, Gianfranco Ciardo, Gerald Lüttgen	Decision-diagram-based techniques for bounded reachability checking of asynchronous systems.	STTT	2009	DBLP DOI BibTeX RDF	Edge-valued decision diagrams, Petri net, Formal verification, BDDs, Reachability analysis, Bounded model checking, Asynchronous design, ADDs
3	Waleed K. Al-Assadi, Sindhu Kakarla	Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits.	J. Electronic Testing	2009	DBLP DOI BibTeX RDF	NULL convention logic (NCL), SCOAP, ATPG, Asynchronous circuits, Design for test (DFT)