Search results for "asynchronous circuit"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Rui Gong, Wei Chen 0009, Fang Liu, Kui Dai, Zhiying Wang	A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	SEE tolerance, SEU tolerance, SET tolerance, Asynchronous circuit
3	Chin-Khai Tang, Chun-Yen Lin, Yi-Chang Lu	An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node.	ISQED	2008	DBLP DOI BibTeX RDF	Asynchronous Circuit Design, Single Track, Dual-Rail, Fast Forwarding
2	Ad M. G. Peeters, Mark de Wit	Asynchronous circuit design using Handshake Solutions.	SoCC	2008	DBLP DOI BibTeX RDF
2	Victor Khomenko, Mark Schäfer, Walter Vogler	Output-Determinacy and Asynchronous Circuit Synthesis.	ACSD	2007	DBLP DOI BibTeX RDF	output-determinacy, OR-causality, decomposition, asynchronous circuits, STG
2	Taeyong Je, Yungseon Eo	Efficient Signal Integrity Verification Method of Multi-Coupled RLC Interconnect Lines with Asynchronous Circuit Switching.	ISQED	2006	DBLP DOI BibTeX RDF
2	Rui Gong, Wei Chen 0009, Fang Liu, Kui Dai, Zhiying Wang	Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique.	DFT	2006	DBLP DOI BibTeX RDF
2	Mark Schäfer, Walter Vogler, Ralf Wollowski, Victor Khomenko	Strategies for Optimised STG Decomposition.	ACSD	2006	DBLP DOI BibTeX RDF	Petri net, decomposition, Asynchronous circuit, STG, speed-independent
2	Signe J. Silver, Janusz A. Brzozowski	True Concurrency in Models of Asynchronous Circuit Behavior.	Formal Methods in System Design	2003	DBLP DOI BibTeX RDF	multiple-winner, single-winner, semi-modular, asynchronous, circuit, interleaving, true concurrency, delay-insensitive
2	Delong Shang, Fei Xia, Alexandre Yakovlev	Asynchronous circuit synthesis via direct translation.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Walter Vogler, Ralf Wollowski	Decomposition in Asynchronous Circuit Design.	FSTTCS	2002	DBLP DOI BibTeX RDF
2	Walter Vogler, Ralf Wollowski	Decomposition in Asynchronous Circuit Design.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF
2	Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken	DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits.	ASYNC	2000	DBLP DOI BibTeX RDF	DUDES, testing, ATPG, fault model, asynchronous circuit, stuck-at fault, fault collapsing
2	Michael J. Liebelt, Cheng-Chew Lim	A method for determining whether asynchronous circuits are self-checking.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise
2	Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar	Initialization issues in asynchronous circuit synthesis.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	asynchronous circuit synthesis, initialization, signal transition graph
2	Jun Gu, Ruchir Puri	Asynchronous circuit synthesis with Boolean satisfiability.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
2	Chantal Ykman-Couvreur, Bill Lin	Optimised state assignment for asynchronous circuit synthesis.	ASYNC	1995	DBLP DOI BibTeX RDF	optimised state assignment, asynchronous circuit synthesis, complete state coding, state graph level, asynchronous benchmarks, circuit area, logic design, encoding, asynchronous circuits, computation time, state assignment
2	Joep L. W. Kessels	VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player.	ASYNC	1995	DBLP DOI BibTeX RDF	digital audio tape, VLSI programming, low-power asynchronous Reed-Solomon decoder, DCC player, Tangram, minimal power dissipation, low-power cost-effective design, VLSI, logic programming, power consumption, power consumption, asynchronous circuits, asynchronous circuit, decoding, Reed-Solomon codes
2	Ganesh Gopalakrishnan, Erik Brunvand, Nick Michell, Steven M. Nowick	A correctness criterion for asynchronous circuit validation and optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
1	Jung-Lin Yang, Shin-Nung Lu, Pei-Hsuan Yu	Asynchronous Circuit Design on Field Programmable Gate Array Devices.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Behnam Ghavami, Hossein Pedram	Low power asynchronous circuit back-end design flow.	Microelectronics Journal	2011	DBLP DOI BibTeX RDF
1	Fataneh Jafari, Mahdi Mosaffa, Siamak Mohammadi	On the Potentials of FinFETs for Asynchronous Circuit Design.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Rui A. L. de Cristo, Ricardo P. Jasinski, Volnei A. Pedroni	Analysis and Preliminary Measurements of Radiated Emissions in an Asynchronous Circuit versus its Synchronous Counterpart.	ReConFig	2010	DBLP DOI BibTeX RDF
1	Ahmad Al Zahrani, Andrew Bailey, Guoyuan Fu, Jia Di	Glitch-free design for multi-threshold CMOS NCL circuits.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	asynchronous circuit, mtcmos, glitch, threshold gate, null convention logic
1	Rajat Subhra Chakraborty, Swarup Bhunia	A study of asynchronous design methodology for robust CMOS-nano hybrid system design.	JETC	2009	DBLP DOI BibTeX RDF	CMOS-nano co-design, dual-rail circuits, logic degradation, nano-scale crossbar, Asynchronous design, robust design, micropipelines
1	Mohsen Raji, Behnam Ghavami, Hossein Pedram	Statistical static performance analysis of asynchronous circuits considering process variation.	ISQED	2009	DBLP DOI BibTeX RDF
1	Gang Jin, Lei Wang 0011, Zhiying Wang	The Design of Asynchronous Microprocessor Based on Optimized NCL_X Design-Flow.	NAS	2009	DBLP DOI BibTeX RDF
1	Andrew Bailey, Ahmad Al Zahrani, Guoyuan Fu, Jia Di, Scott C. Smith	Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power.	J. Low Power Electronics	2008	DBLP DOI BibTeX RDF
1	Nobuo Karaki, Takashi Nanmoto, Satoshi Inoue	An Asynchronous Circuit Design Technique for a Flexible 8-Bit Microprocessor.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Victor Khomenko, Mark Schäfer, Walter Vogler	Output-Determinacy and Asynchronous Circuit Synthesis.	Fundam. Inform.	2008	DBLP BibTeX RDF
1	Fei Qiao, Huazhong Yang, Gang Huang, Hui Wang 0004	Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection.	Science in China Series F: Information Sciences	2008	DBLP DOI BibTeX RDF	low-swing interface, differential signaling, tapered-buffer, interconnect, asynchronous circuit, low power circuit
1	Brian Fett, Marc D. Riedel	Module locking in biochemical synthesis.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Dilip P. Vasudevan, Aristides Efthymiou	A Partial Scan Based Test Generation for Asynchronous Circuits.	DDECS	2008	DBLP DOI BibTeX RDF
1	Morteza Damavandpeyma, Siamak Mohammadi	Architectural Synthesis with Control Data Flow Extraction toward an Asynchronous CAD Tool.	DSD	2008	DBLP DOI BibTeX RDF
1	José Manuel Colmenar, Noelia Morón, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo	Modelling Asynchronous Systems using Probability Distribution Functions.	PDP	2008	DBLP DOI BibTeX RDF	modelling, asynchronous, microarchitecture
1	Cheoljoo Jeong, Steven M. Nowick	Technology Mapping and Cell Merger for Asynchronous Threshold Networks.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Martin Simlastík, Viera Stopjaková	Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey.	PATMOS	2008	DBLP DOI BibTeX RDF	Asynchronous Digital Circuits, Self-time Digital Circuits, Synchronous-to-asynchronous Conversion, DLAP, De-synchronization, Phased Logic, LEDR, Low Power, Null Convention Logic, SADT
1	Koji Ohashi, Mineo Kaneko	Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	high-level synthesis, asynchronous circuit, datapath, register binding
1	Victor Khomenko, Mark Schäfer	Combining Decomposition and Unfolding for STG Synthesis.	ICATPN	2007	DBLP DOI BibTeX RDF	Petri net, decomposition, Asynchronous circuit, unfolding, STG, state space explosion
1	Nam-Phuong D. Nguyen, Hiroyuki Kuwahara, Chris J. Myers, James P. Keener	The Design of a Genetic Muller C-Element.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda	Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Tomohiro Yoneda, Chris J. Myers	Synthesis of Timed Circuits Based on Decomposition.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Gang Jin, Lei Wang 0011, Zhiying Wang, Kui Dai	An Optimal Design Method for De-synchronous Circuit Based on Control Graph.	APPT	2007	DBLP DOI BibTeX RDF	de-synchronous, control graph, performance evaluation, algorithm, Petri-net, asynchronous
1	Jian Ruan, Zhiying Wang, Kui Dai, Yong Li 0006	Design and Test of Self-checking Asynchronous Control Circuit.	PATMOS	2007	DBLP DOI BibTeX RDF
1	Xu Wang, Marta Z. Kwiatkowska, Georgios K. Theodoropoulos, Qianyi Zhang	Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs.	Electr. Notes Theor. Comput. Sci.	2006	DBLP DOI BibTeX RDF
1	Janusz A. Brzozowski	Topics in Asynchronous Circuit Theory.	Recent Advances in Formal Languages and Applications	2006	DBLP DOI BibTeX RDF
1	R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, André Inácio Reis	Asynchronous circuit design on reconfigurable devices.	SBCCI	2006	DBLP DOI BibTeX RDF	FPGAs, asynchronous circuits
1	Eun-Ju Choi, Kyoung-Rok Cho, Je-Hoon Lee	New Data Encoding Method with a Multi-Value Logic for Low Power Asynchronous Circuit Design.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Ad M. G. Peeters	Clockless IC design using handshake technology.	ISPD	2006	DBLP DOI BibTeX RDF
1	Jun Xu, Reza Sotudeh, Mark B. Josephs	Asynchronous Packet-Switching for Networks-on-Chip.	ACSD	2006	DBLP DOI BibTeX RDF
1	Cheoljoo Jeong, Steven M. Nowick	Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Song Peng, Rajit Manohar	Self-Healing Asynchronous Arrays.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Martin Delvai, Andreas Steininger	Solving the Fundamental Problem of Digital Design - A Systematic Review of Design Methods.	DSD	2006	DBLP DOI BibTeX RDF
1	Lei Wang 0011, Zhiying Wang, Kui Dai	An Approximate Method for Performance Evaluation of Asynchronous Pipeline Rings.	CIT	2006	DBLP DOI BibTeX RDF
1	Sangyun Kim, Peter A. Beerel	Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Luis A. Plana, Sam Taylor, Doug A. Edwards	Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance.	ICCD	2005	DBLP DOI BibTeX RDF
1	Walter Vogler, Ben Kangsah	Improved Decomposition of STGs.	ACSD	2005	DBLP DOI BibTeX RDF
1	Nikolai Starodoubtsev, Sergei Bystrov	Behavior and Synthesis of Two-Input Gate Asynchronous Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
1	H. Nagasaka, T. Sato, T. Sugiura, E. Otobe, M. Hasegawa, K. Tanji, N. Otani, T. Shimamori	The modem for ultra-wideband communication employing surface-acoustic-wave devices.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Lilian Janin, Doug Edwards	Software Visualisation Techniques Adapted and Extended for Asynchronous Hardware Design.	IV	2005	DBLP DOI BibTeX RDF	program comprehension, asynchronous circuits, Software visualisation, coordinated views
1	Nitin Gupta, Doug A. Edwards	Synthesis of Asynchronous Circuits Using Early Data Validity.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Tobias Bjerregaard, Shankar Mahadevan, Jens Sparsø	A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Chun-Pong Yu, Chiu-sing Choy, Hao Min, Cheong-fat Chan, Kong-Pang Pun	A low power asynchronous Java processor for contactless smart card.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers	Synthesis of Speed Independent Circuits Based on Decomposition.	ASYNC	2004	DBLP DOI BibTeX RDF	abstraction, synthesis, Decomposition, STGs, speed-independent circuits
1	Alex Branover, Rakefet Kol, Ran Ginosar	Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones.	DATE	2004	DBLP DOI BibTeX RDF
1	Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou	Coping with The Variability of Combinational Logic Delays.	ICCD	2004	DBLP DOI BibTeX RDF
1	Jeong-Gun Lee, Euiseok Kim, Jeong-A. Lee, Eunok Paek	Efficient Buffer Allocation for Asynchronous Linear Pipelines by Design Space Localization.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
1	Delong Shang, Frank P. Burns, Alexandre V. Bystrov, Albert Koelmans, Danil Sokolov, Alexandre Yakovlev	A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Kamel Slimani, Yann Rémond, Gilles Sicard, Marc Renaudin	TAST Profiler and Low Energy Asynchronous Design Methodology.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Sirianni	Validation of asynchronous circuit specifications using IF/CADP.	VLSI-SOC	2003	DBLP BibTeX RDF
1	Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Sirianni	An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. (PDF / PS)	HICSS	2003	DBLP DOI BibTeX RDF
1	Dominique Borrione, Menouer Boubekeur	Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications.	FDL	2003	DBLP BibTeX RDF
1	Agnes Madalinski, Alexandre V. Bystrov, Victor Khomenko, Alexandre Yakovlev	Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design.	DATE	2003	DBLP DOI BibTeX RDF
1	Agnes Madalinski	CONFRES: Interactive Coding Conflict Resolver Based on Core Visualisation.	ACSD	2003	DBLP DOI BibTeX RDF
1	Alexandre V. Bystrov, Danil Sokolov, Alexandre Yakovlev	Low-Latency Contro Structures with Slack.	ASYNC	2003	DBLP DOI BibTeX RDF
1	Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya	Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions.	ASYNC	2003	DBLP DOI BibTeX RDF
1	Oliver Kraus, Martin Padeffke	XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines.	DATE	2003	DBLP DOI BibTeX RDF
1	Hing-mo Lam, Chi-Ying Tsui	High performance and low power completion detection circuit.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Artur Pereira, Antonio Rui Borges, Antonio Ferrari	Exclusion Relation of k Out of n and the Synthesis of Speed-Independent Circuits.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev	Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris J. Myers	Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method.	PRDC	2002	DBLP DOI BibTeX RDF
1	Alexandre V. Bystrov, Alexandre Yakovlev	Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment.	ASYNC	2002	DBLP BibTeX RDF
1	Agnes Madalinski, Alexandre V. Bystrov, Alexandre Yakovlev	Visualization of Coding Conflicts in Asynchronous Circuit Design.	IWLS	2002	DBLP BibTeX RDF
1	Josep Carmona, Jordi Cortadella, Enric Pastor	Synthesis of Reactive Systems: Application to Asynchronous Circuit Design.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF
1	Christos P. Sotiriou	Implementing asynchronous circuits using a conventional EDA tool-flow.	DAC	2002	DBLP DOI BibTeX RDF	tool-flow, asynchronous, EDA
1	Paul I. Pénzes, Alain J. Martin	An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor.	DATE	2002	DBLP DOI BibTeX RDF
1	Peter A. Beerel, Aiguo Xie	Performance Analysis of Asynchronous Circuits Using Markov Chains.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF
1	Victor Varshavsky, Vyacheslav Marakhovsky	GALA (Globally Asynchronous - Locally Arbitrary) Design.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF
1	Chris J. Myers	Asynchronous circuit design.		2001	RDF
1	Oscar Garnica, Juan Lanchares, Román Hermida	Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation.	ACSD	2001	DBLP DOI BibTeX RDF
1	Pui-Lam Siu, Chiu-sing Choy, Jan Butas, Cheong-fat Chan	A low power asynchronous DES.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Eric Keller	Building Asynchronous Circuits with JBits.	FPL	2001	DBLP DOI BibTeX RDF
1	Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev	Hardware and Petri Nets: Application to Asynchronous Circuit Design.	ICATPN	2000	DBLP DOI BibTeX RDF
1	Nikolai Starodoubtsev, Alexandre V. Bystrov, Alexandre Yakovlev	Semi-modular Latch Chains for Asynchronous Circuit Design.	PATMOS	2000	DBLP DOI BibTeX RDF
1	Joep L. W. Kessels, Gerrit den Besten, Ad M. G. Peeters, Torsten Kramer, Volker Timm	Applying Asynchronous Circuits in Contactless Smart Cards.	ASYNC	2000	DBLP DOI BibTeX RDF	low-power asynchronous circuits, contactless devices, DES cryptography, smart cards
1	Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri	CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder.	ASYNC	2000	DBLP DOI BibTeX RDF	pulse logic, switch-level fault simulation, Cellular Automata, BIST, asynchronous circuits, testability, stuck-at faults, domino logic, self-timed circuits, dynamic circuits
1	Eric Senn, Bertrand Zavidovique	Examples of Image Processing to Benefit from an Asynchronous Implementation.	CAMP	2000	DBLP DOI BibTeX RDF	asynchronous implementation, machine architecture, router circuit, self-timed design, image processing, image processing, VLSI implementation, communication performances, salient features
1	Mohit Sahni, Takashi Nanya	On the CSC Property of Signal Transition Graph Specifications for Asynchronous Circuit Design.	ASP-DAC	1998	DBLP BibTeX RDF
1	Yoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya	Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic.	ASYNC	1998	DBLP DOI BibTeX RDF	pulse-driven logic, Josephson junction device, RSFQ device, pipeline, asynchronous circuit, delay-insensitive circuit
1	Michael V. Goncharov, Alexander B. Smirnov, Nikolai Starodoubtsev, Ilya V. Klotchkov	Timing Extensions of STG Model and a Method to Simulate Timed STG Behavior in VHDL Environment.	ACSD	1998	DBLP DOI BibTeX RDF	asynchronous circuits' design, simulation, VHDL, Signal Transition Graph (STG)
1	Tomohiro Yoneda, Yutaka Ohtsuka, Märt Saarepera	Verification of Parameterized Asynchronous Circuits: A Case Study.	ACSD	1998	DBLP DOI BibTeX RDF	parameterized asynchronous circuits, ACTL model checking, Formal verification, abstraction, PVS