Search results for "asynchronous circuits"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Frank te Beest, Kees van Berkel, Ad M. G. Peeters	Adding Synchronous and LSSD Modes to Asynchronous Circuits.	ASYNC	2002	DBLP DOI BibTeX RDF	design for testability, asynchronous circuits, scan test, LSSD
4	Joep L. W. Kessels, Gerrit den Besten, Ad M. G. Peeters, Torsten Kramer, Volker Timm	Applying Asynchronous Circuits in Contactless Smart Cards.	ASYNC	2000	DBLP DOI BibTeX RDF	low-power asynchronous circuits, contactless devices, DES cryptography, smart cards
4	Rik van de Wiel	High-level test evaluation of asynchronous circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	high-level test evaluation, production fault tests, high-level circuit description, asynchronous 22 k transistor DCC error corrector IC, VLSI, logic testing, fault model, asynchronous circuits, asynchronous circuits, error detection codes
4	Eckhard Grass, S. Jones	Asynchronous circuits based on multiple localised current-sensing completion detection.	ASYNC	1995	DBLP DOI BibTeX RDF	dual rail coding, Current-Sensing Completion Detection, Current-Sensing Circuits, logic design, power consumption, asynchronous circuits, asynchronous circuits, granularity, parallel multiplier, BiCMOS
4	Ding Lu, Carol Q. Tong	High level fault modeling of asynchronous circuits.	VTS	1995	DBLP DOI BibTeX RDF	high level fault modeling, transitional fault models, stuck-at-false model, stuck-at-true model, fault diagnosis, logic testing, timing, asynchronous circuits, asynchronous circuits, signal transition graph, signal flow graphs, self-timed circuits
4	Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng	Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.	VLSI Design	1995	DBLP DOI BibTeX RDF	stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions
3	Mehrdad Najibi, Kamran Saleh, Hossein Pedram	Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	quasi-delay insensitive, standard-cell layout, asynchronous circuits
3	Mark B. Josephs	Gate-level modelling and verification of asynchronous circuits using CSPM and FDR.	ASYNC	2007	DBLP DOI BibTeX RDF
3	Frankie Liu, Ron Ho, Robert J. Drost, Scott Fairbanks	On-chip samplers for test and debug of asynchronous circuits.	ASYNC	2007	DBLP DOI BibTeX RDF
3	G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin	Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits.	CHES	2006	DBLP DOI BibTeX RDF	QDI Asynchronous circuits, Path Swapping (PS), Power analysis
3	Nikolai Starodoubtsev, Sergei Bystrov	Behavior and Synthesis of Two-Input Gate Asynchronous Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
3	Yannick Monnet, Marc Renaudin, Régis Leveugle	Asynchronous circuits transient faults sensitivity evaluation.	DAC	2005	DBLP DOI BibTeX RDF	quasi delay insensitive, simulation, fault model, asynchronous circuits, transient fault
3	Victor Khomenko, Maciej Koutny, Alexandre Yakovlev	Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT.	ACSD	2004	DBLP DOI BibTeX RDF	net unfoldings, partial order techniques, Petri nets, logic synthesis, asynchronous circuits, SAT, signal transition graphs, STG, self-timed circuits
3	Masashi Imai, Metehan Özcan, Takashi Nanya	Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model.	ASYNC	2004	DBLP DOI BibTeX RDF
3	Mark B. Josephs	An Analysis of Determinacy Using a Trace-Theoretic Model of Asynchronous Circuits.	ASYNC	2003	DBLP DOI BibTeX RDF
3	Arash Saifhashemi, Hossein Pedram	Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction.	DAC	2003	DBLP DOI BibTeX RDF	CHP, PLI, CSP, asynchronous circuits, channel, verilog
3	Jacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert D. Mullins, George S. Taylor	Security Evaluation of Asynchronous Circuits.	CHES	2003	DBLP DOI BibTeX RDF	Dual-Rail encoding, EMA, Design-time security evaluation, Asynchronous circuits, Power Analysis, Fault Analysis
3	Amy Streich, Alex Kondratyev, Lief Sorensen	Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach.	ASYNC	2002	DBLP DOI BibTeX RDF	ATPG, asynchronous circuits, stuck-at faults, partial scan
3	Ivan E. Sutherland, Jon K. Lexau	Designing Fast Asynchronous Circuits.	ASYNC	2001	DBLP DOI BibTeX RDF
3	Michael J. Liebelt, Cheng-Chew Lim	A method for determining whether asynchronous circuits are self-checking.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, TSC, low noise properties, semi-modular asynchronous circuit, output stuck-at-faults, low power, fault diagnosis, logic testing, integrated circuit testing, design for testability, asynchronous circuits, testability, totally self-checking, integrated circuit noise
3	Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken	DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits.	ASYNC	2000	DBLP DOI BibTeX RDF	DUDES, testing, ATPG, fault model, asynchronous circuit, stuck-at fault, fault collapsing
3	Marly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri	CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder.	ASYNC	2000	DBLP DOI BibTeX RDF	pulse logic, switch-level fault simulation, Cellular Automata, BIST, asynchronous circuits, testability, stuck-at faults, domino logic, self-timed circuits, dynamic circuits
3	Per Arne Karlsen, Per Torstein Røine	A Timing Verifier and Timing Profiler for Asynchronous Circuits.	ASYNC	1999	DBLP DOI BibTeX RDF
3	Z. John Deng, Steve R. Whiteley, Theodore Van Duzer, José A. Tierno	Asynchronous Circuits and Systems in Superconducting RSFQ Digital Technology.	ASYNC	1998	DBLP DOI BibTeX RDF
3	Radu Negulescu, Ad M. G. Peeters	Verification of Speed-Dependences in Single-Rail Handshake Circuits.	ASYNC	1998	DBLP DOI BibTeX RDF	single-rail, isochronic forks, verification, timing, asynchronous circuits, progress, speed-independent circuits, process spaces, handshake circuits
3	Jo C. Ebergen, Robert Berks	Response Time Properties of Some Asynchronous Circuits.	ASYNC	1997	DBLP DOI BibTeX RDF	variable-delay model, performance analysis, Asynchronous circuits, response time, micropipeline
3	Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni	On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic.	ASYNC	1997	DBLP DOI BibTeX RDF
3	Ajay Khoche, Erik Brunvand	Critical hazard free test generation for asynchronous circuits.	VTS	1997	DBLP DOI BibTeX RDF	self-timed control circuits, critical hazard-free tests, six-valued algebra, macro-module library, partial scan based DFT environment, unbounded delay model, asynchronous circuits, asynchronous circuits, D-algorithm
3	Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin	Partial scan delay fault testing of asynchronous circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	robust path delay fault testing, asynchronous circuits, delay faults, sequential testing
3	Wendy Belluomini, Chris J. Myers	Efficient Timing Analysis Algorithms for Timed State Space Exploration.	ASYNC	1997	DBLP DOI BibTeX RDF	timing analysis algorithms, timed state space exploration, timed circuit synthesis, geometric regions, computational complexity, timing, asynchronous circuits, partial orders
3	Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng	Automatic synthesis of gate-level timed circuits with choice.	ARVLSI	1995	DBLP DOI BibTeX RDF	gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates
3	Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia, Angel Barriga Barros, Raúl Jiménez, José L. Huertas	New CMOS VLSI linear self-timed architectures.	ASYNC	1995	DBLP DOI BibTeX RDF	semiconductor storage, CMOS VLSI linear self-timed architectures, digital signal processor circuits, self-timed techniques, synchronous VLSI circuits, FIFO memories, VLSI, asynchronous circuits, asynchronous circuits, digital signal processing chips, CMOS memory circuits, hardware resources
3	Kees van Berkel, Ferry Huberts, Ad M. G. Peeters	Stretching quasi delay insensitivity by means of extended isochronic forks.	ASYNC	1995	DBLP DOI BibTeX RDF	extended isochronic forks, isochronic-fork assumption, double-rail data paths, DCC error decoder, logic design, asynchronous circuits, asynchronous circuits, arbiter, delay insensitivity, handshake circuits
3	Chris J. Myers, Peter A. Beerel, Teresa H. Y. Meng	Technology mapping of timed circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	gate library, C-elements, ATACS, timing, logic design, logic CAD, asynchronous circuits, asynchronous circuits, timing information, AND gates, synthesis tool, OR gates, timed circuits
3	Ad M. G. Peeters, Kees van Berkel	Single-rail handshake circuits.	ASYNC	1995	DBLP DOI BibTeX RDF	single-rail handshake circuits, four-phase handshake protocol, standard-cell library, technology migration, low-power applications, VLSI, protocols, energy-efficient, asynchronous circuits, asynchronous circuits, integrated logic circuits, cellular arrays
3	Garth Baulch, David Hemmendinger, Cherrice Traver	Analyzing and verifying locally clocked circuits with the concurrency workbench.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	locally clocked circuits, concurrency workbench, synchronous computational elements, concurrent system modelling, CCS process algebra, formal verification, timing, logic design, process algebra, logic CAD, asynchronous circuits, asynchronous circuits, circuit analysis computing, asynchronous communication
3	Chantal Ykman-Couvreur, Bill Lin	Efficient state assignment framework for asynchronous state graphs. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	state assignment framework, asynchronous state graphs, state graph level, complete state coding problem, circuit area, logic design, encoding, asynchronous circuits, asynchronous circuits, computation time, state assignment
2	Victor Khomenko	Logic Decomposition of Asynchronous Circuits Using STG Unfoldings.	ASYNC	2011	DBLP DOI BibTeX RDF
2	Evriklis Kounalakis, Christos P. Sotiriou	CPlace: A Constructive Placer for Synchronous and Asynchronous Circuits.	ASYNC	2011	DBLP DOI BibTeX RDF
2	Carlos Ortega, Jonathan Tse, Rajit Manohar	Static Power Reduction Techniques for Asynchronous Circuits.	ASYNC	2010	DBLP DOI BibTeX RDF
2	Feng Shi, Yiorgos Makris	Enhancing Simulation Accuracy through Advanced Hazard Detection in Asynchronous Circuits.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
2	Mohsen Raji, Behnam Ghavami, Hossein Pedram	Statistical static performance analysis of asynchronous circuits considering process variation.	ISQED	2009	DBLP DOI BibTeX RDF
2	Waleed K. Al-Assadi, Sindhu Kakarla	Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits.	J. Electronic Testing	2009	DBLP DOI BibTeX RDF	NULL convention logic (NCL), SCOAP, ATPG, Asynchronous circuits, Design for test (DFT)
2	Martin Simlastík, Viera Stopjaková	Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey.	PATMOS	2008	DBLP DOI BibTeX RDF	Asynchronous Digital Circuits, Self-time Digital Circuits, Synchronous-to-asynchronous Conversion, DLAP, De-synchronization, Phased Logic, LEDR, Low Power, Null Convention Logic, SADT
2	Sharareh Zamanzadeh, Mohammad Mirza-Aghatabar, Mehrdad Najibi, Hossein Pedram, Abolghasem Sadeghi	Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations.	DSD	2008	DBLP DOI BibTeX RDF
2	Behnam Ghavami, Mehrshad Khosraviani, Hossein Pedram	Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing.	DSD	2008	DBLP DOI BibTeX RDF
2	Dilip P. Vasudevan, Aristides Efthymiou	A Partial Scan Based Test Generation for Asynchronous Circuits.	DDECS	2008	DBLP DOI BibTeX RDF
2	Feng Shi	Removing hazards in multi-level logic optimization for generalized fundamental-mode asynchronous circuits.	ICCD	2008	DBLP DOI BibTeX RDF
2	Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda	Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Mehrdad Najibi, Mahtab Niknahad, Hossein Pedram	Performance Evaluation of Asynchronous Circuits with Choice Using Abstract Probabilistic Timed Petri Nets.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Mahtab Niknahad, Behnam Ghavami, Mehrdad Najibi, Hossein Pedram	A Power Estimation Methodology for QDI Asynchronous Circuits based on High-Level Simulation.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Behnam Ghavami, Mahtab Niknahad, Mehrdad Najibi, Hossein Pedram	A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits.	PATMOS	2007	DBLP DOI BibTeX RDF
2	Frédéric Béal, Tomohiro Yoneda, Chris J. Myers	Hazard Checking of Timed Asynchronous Circuits Revisited.	ACSD	2007	DBLP DOI BibTeX RDF
2	Cheoljoo Jeong, Steven M. Nowick	Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation.	ASP-DAC	2007	DBLP DOI BibTeX RDF
2	Takao Konishi, Naohiro Hamada, Hiroshi Saito	A Control Circuit Synthesis Method for Asynchronous Circuits in Bundled-Data Implementation.	CIT	2007	DBLP DOI BibTeX RDF
2	Pankaj Golani, Georgios D. Dimou, Mallika Prakash, Peter A. Beerel	Design of a High-Speed Asynchronous Turbo Decoder.	ASYNC	2007	DBLP DOI BibTeX RDF
2	Nam-Phuong D. Nguyen, Hiroyuki Kuwahara, Chris J. Myers, James P. Keener	The Design of a Genetic Muller C-Element.	ASYNC	2007	DBLP DOI BibTeX RDF
2	Nikolaos Minas, David Kinniment, Keith Heron, Gordon Russell	A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability.	ASYNC	2007	DBLP DOI BibTeX RDF
2	Sangyun Kim, Peter A. Beerel	Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou	Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
2	Xu Wang, Marta Z. Kwiatkowska	On process-algebraic verification of asynchronous circuits.	ACSD	2006	DBLP DOI BibTeX RDF
2	Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya	ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation.	CIT	2006	DBLP DOI BibTeX RDF
2	Yu Zhou, Danil Sokolov, Alexandre Yakovlev	Cost-aware synthesis of asynchronous circuits based on partial acknowledgement.	ICCAD	2006	DBLP DOI BibTeX RDF
2	Ferdinand Peper	Asynchronous Architectures for Nanometer Scales.	ASYNC	2006	DBLP DOI BibTeX RDF
2	Song Peng, Rajit Manohar	Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	asynchronous circuits, yield, defect tolerance, 3D integration, self-reconfiguration
2	Feng Shi, Yiorgos Makris	Testing delay faults in asynchronous handshake circuits.	ICCAD	2006	DBLP DOI BibTeX RDF	test generation, asynchronous circuits, delay faults, handshake circuits
2	R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, André Inácio Reis	Asynchronous circuit design on reconfigurable devices.	SBCCI	2006	DBLP DOI BibTeX RDF	FPGAs, asynchronous circuits
2	Yannick Monnet, Marc Renaudin, Régis Leveugle	Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	quasi-delay insensitive, hardening techniques, Asynchronous circuits, data encryption standard, fault attacks
2	Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers	High Level Synthesis of Timed Asynchronous Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
2	Nitin Gupta, Doug A. Edwards	Synthesis of Asynchronous Circuits Using Early Data Validity.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Deepali Koppad, Alexandre V. Bystrov, Alexandre Yakovlev	Off-Line Testing of Asynchronous Circuits.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain	DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement.	DATE	2005	DBLP DOI BibTeX RDF
2	Song Peng, Rajit Manohar	Efficient Failure Detection in Pipelined Asynchronous Circuits.	DFT	2005	DBLP DOI BibTeX RDF
2	Delong Shang, Alexandre V. Bystrov, Alexandre Yakovlev, Deepali Koppad	On-Line Testing of Globally Asynchronous Circuits.	IOLTS	2005	DBLP DOI BibTeX RDF
2	Yannick Monnet, Marc Renaudin, Régis Leveugle	Hardening Techniques against Transient Faults for Asynchronous Circuits.	IOLTS	2005	DBLP DOI BibTeX RDF
2	Konrad J. Kulikowski, Ming Su, Alexander B. Smirnov, Alexander Taubin, Mark G. Karpovsky, Daniel MacDonald	Delay Insensitive Encoding and Power Analysis: A Balancing Act.	ASYNC	2005	DBLP DOI BibTeX RDF
2	Wonjin Jang, Alain J. Martin	SEU-Tolerant QDI Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
2	Lilian Janin, Doug Edwards	Software Visualisation Techniques Adapted and Extended for Asynchronous Hardware Design.	IV	2005	DBLP DOI BibTeX RDF	program comprehension, asynchronous circuits, Software visualisation, coordinated views
2	Matthew L. King, Kewal K. Saluja	Testing Micropipelined Asynchronous Circuits.	ITC	2004	DBLP DOI BibTeX RDF
2	S. F. Nielsen, Jens Sparsø, Jan Madsen	Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation.	DSD	2004	DBLP DOI BibTeX RDF
2	Radu Negulescu	General Testers for Asynchronous Circuits.	ASYNC	2004	DBLP DOI BibTeX RDF
2	Aristides Efthymiou, Christos P. Sotiriou, Douglas A. Edwards	Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits.	DATE	2004	DBLP DOI BibTeX RDF
2	Sarah Thompson, Alan Mycroft	Abstract Interpretation of Combinational Asynchronous Circuits.	SAS	2004	DBLP DOI BibTeX RDF
2	Yannick Monnet, Marc Renaudin, Régis Leveugle	Asynchronous Circuits Sensitivity to Fault Injection.	IOLTS	2004	DBLP DOI BibTeX RDF
2	Ivan Blunno, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, Christos P. Sotiriou	Handshake Protocols for De-Synchronization.	ASYNC	2004	DBLP DOI BibTeX RDF
2	Alireza Kaviani	Phase Alignment Using Asynchronous State Machines.	ASYNC	2004	DBLP DOI BibTeX RDF
2	Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida	Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization.	PATMOS	2003	DBLP DOI BibTeX RDF
2	Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda	Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits.	ICCAD	2003	DBLP DOI BibTeX RDF
2	Nikolai Starodoubtsev, Sergei Bystrov, Alexandre Yakovlev	Monotonic Circuits with Complete Acknowledgement.	ASYNC	2003	DBLP DOI BibTeX RDF
2	Menahem Lowy, Neal Butler, Rosanne Tinkler	Low power VLSI sequential circuit architecture using critical race control.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	critical races, low-power VLSI circuits, asynchronous circuits
2	Victor Khomenko, Maciej Koutny, Alexandre Yakovlev	Detecting State Coding Conflicts in STG Unfoldings Using SAT.	ACSD	2003	DBLP DOI BibTeX RDF	complete state coding, CSC, net unfoldings, Petri nets, asynchronous circuits, SAT, signal transition graphs, STG, automated synthesis
2	Frank te Beest, Ad M. G. Peeters, Kees van Berkel, Hans G. Kerkhoff	Synchronous Full-Scan for Asynchronous Handshake Circuits.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	L1L2*, DFT, asynchronous circuits, scan design, LSSD
2	Alex Kondratyev, Kelvin Lwin	Design of Asynchronous Circuits Using Synchronous CAD Tools.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
2	Peter A. Beerel	Asynchronous Circuits: An Increasingly Practical Design Solution (invited). (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF
2	Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland	Implementing Asynchronous Circuits on LUT Based FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
2	Oscar Garnica, Juan Lanchares, Román Hermida	A New Methodology to Design Low-Power Asynchronous Circuits.	PATMOS	2002	DBLP DOI BibTeX RDF
2	Alex Kondratyev, Kelvin Lwin	Design of asynchronous circuits by synchronous CAD tools.	DAC	2002	DBLP DOI BibTeX RDF
2	Christos P. Sotiriou	Implementing asynchronous circuits using a conventional EDA tool-flow.	DAC	2002	DBLP DOI BibTeX RDF	tool-flow, asynchronous, EDA
2	Thomas Verdel, Yiorgos Makris	Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies. (PDF / PS)	DFT	2002	DBLP DOI BibTeX RDF
2	Peter A. Beerel, Aiguo Xie	Performance Analysis of Asynchronous Circuits Using Markov Chains.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF