Search results for "asynchronous logic"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Hemangee K. Kapoor, Mark B. Josephs	Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis.	DAC	2004	DBLP DOI BibTeX RDF	asynchronous logic synthesis, delay-insensitive decomposition
3	David A. Kearney, Neil W. Bergmann	Performance evaluation of asynchronous logic pipelines with data dependent processing delays.	ASYNC	1995	DBLP DOI BibTeX RDF	asynchronous logic pipelines, data dependent processing delays, logic stages, data dependent delay, two valued random variable, performance evaluation, performance evaluation, asynchronous circuits, pipeline processing, latches
2	Neil Gershenfeld, David Dalrymple, Kailiang Chen, Ara Knaian, Forrest Green, Erik D. Demaine, Scott Greenwald, Peter Schmidt-Nielsen	Reconfigurable asynchronous logic automata: (RALA).	POPL	2010	DBLP DOI BibTeX RDF	reconfigurable, logic, asynchronous, automata
2	Yannick Monnet, Marc Renaudin, Régis Leveugle	Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	quasi-delay insensitive, hardening techniques, Asynchronous circuits, data encryption standard, fault attacks
2	Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin	State-holding in Look-Up Tables: application to asynchronous logic.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
2	Song Peng, Rajit Manohar	Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	asynchronous circuits, yield, defect tolerance, 3D integration, self-reconfiguration
2	N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin	FPGA Architecture for Multi-Style Asynchronous Logic.	DATE	2005	DBLP DOI BibTeX RDF
2	Mark B. Josephs, Dennis P. Furey	A Programming Approach to the Design of Asynchronous Logic Blocks.	Concurrency and Hardware Design	2002	DBLP DOI BibTeX RDF
2	Georgios K. Theodoropoulos, J. V. Woods	Simulating Asynchronous Architectures on Transputer Networks.	PDP	1996	DBLP DOI BibTeX RDF	asynchronous architecture simulation, asynchronous design techniques, clock related timing problems, CSP based parallel language, asynchronous architectural simulation models, parallel architectures, logic design, asynchronous circuits, circuit analysis computing, parallel languages, Occam, Occam, asynchronous logic, transputer systems, transputer networks
1	Peter Schmidt-Nielsen, Kailiang Chen, Jonathan Bachrach, Scott Greenwald, Forrest Green, Neil Gershenfeld	Cryptography with Asynchronous Logic Automata.	Cryptography and Security	2012	DBLP DOI BibTeX RDF
1	Neil Gershenfeld	Aligning the representation and reality of computation with asynchronous logic automata.	Computing	2011	DBLP DOI BibTeX RDF
1	Danny Dolev, Matthias Függer, Christoph Lenzen, Ulrich Schmid	Fault-tolerant Algorithms for Tick-Generation in Asynchronous Logic: Robust Pulse Generation	CoRR	2011	DBLP BibTeX RDF
1	Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, Yin Sun, Kok-Leong Chang	Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Danny Dolev, Matthias Függer, Christoph Lenzen, Ulrich Schmid	Fault-Tolerant Algorithms for Tick-Generation in Asynchronous Logic: Robust Pulse Generation - [Extended Abstract].	SSS	2011	DBLP DOI BibTeX RDF
1	Michael Robinson	Asynchronous logic circuits and sheaf obstructions	CoRR	2010	DBLP BibTeX RDF
1	Igor Lemberski, Petr Fiser	Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints.	DSD	2010	DBLP DOI BibTeX RDF
1	Babak Rahbaran, Andreas Steininger	Is Asynchronous Logic More Robust Than Synchronous Logic?.	IEEE Trans. Dependable Sec. Comput.	2009	DBLP DOI BibTeX RDF
1	Yvain Thonnart, Edith Beigné, Alexandre Valentian, Pascal Vivet	Power Reduction of Asynchronous Logic Circuits Using Activity Detection.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Tong Lin, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang	Fine-grained Power Gating for Leakage and Short-circuit Power Reduction by using Asynchronous-logic.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Marcus Jeitler, Jakob Lechner	Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation.	ReConFig	2009	DBLP DOI BibTeX RDF	Four State Logic, Asynchronous Processor Design, Fault Injection, Asynchronous Design
1	Alain J. Martin	Asynchronous logic for high variability nano-CMOS.	ICECS	2009	DBLP DOI BibTeX RDF
1	Andrew Bardsley, Luis A. Tarazona, Doug A. Edwards	Teak: A Token-Flow Implementation for the Balsa Language.	ACSD	2009	DBLP DOI BibTeX RDF	logic synthesis, asynchronous logic
1	Charlie Brej, Doug Edwards	Forward and backward guarding in early output logic.	DDECS	2009	DBLP DOI BibTeX RDF
1	Mohsen Raji, Behnam Ghavami, Hossein Pedram	Statistical static performance analysis of asynchronous circuits considering process variation.	ISQED	2009	DBLP DOI BibTeX RDF
1	David Dalrymple, Neil Gershenfeld, Kailiang Chen	Asynchronous logic automata.	Automata	2008	DBLP BibTeX RDF
1	Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach	A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.	NOCS	2008	DBLP DOI BibTeX RDF	NoC testing, QDI asynchronous logic, Network-on-Chip, DfT, testability, NoC, Design-for-Test, GALS, SoC testing, testing methodology, on-chip communication, Globally Asynchronous - Locally Synchronous
1	David Barnhart, Tanya Vladimirova, Martin Sweeting	Design of self-powered wireless system-on-a-chip sensor nodes for hostile environments.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Kok-Leong Chang, Bah-Hwee Gwee, Yuanjin Zheng	A semi-custom memory design for an asynchronous 8051 microcontroller.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Kok-Leong Chang, Yao Zhu, Bah-Hwee Gwee	De-synchronization of a point-of-sales digital-logic controller.	ISCAS	2008	DBLP DOI BibTeX RDF
1	N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin	FPGA Architecture for Multi-Style Asynchronous Logic	CoRR	2007	DBLP BibTeX RDF
1	Scott C. Smith	Design of a logic element for implementing an asynchronous FPGA.	FPGA	2007	DBLP DOI BibTeX RDF	NULL convention logic (NCL), asynchronous logic design, field programmable gate array (FPGA), reconfigurable logic, delay-insensitive circuits
1	Mark B. Josephs	Gate-level modelling and verification of asynchronous circuits using CSPM and FDR.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Thomas Panhofer, Martin Delvai	Self-Healing Circuits for Space-Applications.	FPL	2007	DBLP DOI BibTeX RDF
1	Muhammad Arsalan, Maitham Shams	Asynchronous Adiabatic Logic.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Xuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrand, Vincent Beroulle, Chantal Robach	Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip.	NOCS	2007	DBLP DOI BibTeX RDF
1	Yijun Liu, Zhenkun Li, Pinghua Chen, Guangcong Liu	Power-Efficient Asynchronous Design.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	D. Caucheteux, Edith Beigné, Elisabeth Crochon, Marc Renaudin	AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Kok-Leong Chang, Bah-Hwee Gwee	A low-energy low-voltage asynchronous 8051 microcontroller core.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Alain J. Martin	Can Asynchronous Techniques Help the SoC Designer?	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Jovan Dj. Golic	New Methods for Digital Generation and Postprocessing of Random Data.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	sequential circuits, linear feedback shift registers, integrated circuits, Random number generation, ring oscillators, special-purpose hardware, chaotic systems
1	Eslam Yahya, Marc Renaudin	QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Duarte Lopes de Oliveira, Marius Strum, Wang Jiang Chau	Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers.	SBCCI	2005	DBLP DOI BibTeX RDF	burst-mode, automatic synthesis, hazard, asynchronous logic, speed-independent
1	Justin Hensley, Montek Singh, Anselmo Lastra	A fast, energy-efficient z-comparator.	Graphics Hardware	2005	DBLP DOI BibTeX RDF
1	Hemangee K. Kapoor, Mark B. Josephs	Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation.	ACSD	2005	DBLP DOI BibTeX RDF
1	C. Brej, Jim D. Garside	A Quasi-Delay-Insensitive Method to Overcome Transistor Variation.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard	Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
1	Yijun Liu, Stephen B. Furber	The design of a low power asynchronous multiplier.	ISLPED	2004	DBLP DOI BibTeX RDF	Booth's algorithm, low power, benchmark, multiplier, asynchronous logic
1	John Teifel, Rajit Manohar	Highly pipelined asynchronous FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF	concurrency, pipelining, asynchronous circuits, programmable logic, correctness by construction
1	Simon W. Moore, Ross J. Anderson, Robert D. Mullins, George S. Taylor, Jacques J. A. Fournier	Balanced self-checking asynchronous logic for smart card applications.	Microprocessors and Microsystems	2003	DBLP DOI BibTeX RDF
1	John Morris	Reconfigurable Logic: A Saviour for Experimental Computer Architecture Research.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF	programmable hardware, data flow, stereo correspondence, Reconfigurable logic, asynchronous logic
1	Stephen H. Unger	Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors.	IEEE Design & Test of Computers	2003	DBLP DOI BibTeX RDF
1	John Teifel, Rajit Manohar	Programmable Asynchronous Pipeline Arrays.	FPL	2003	DBLP DOI BibTeX RDF
1	Harri Lampinen, Olli Vainio	Current-sensing completion detection method for standard cell based digital system design.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Ross Smith, Michiel M. Ligthart	High-level design for asynchronous logic.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Euiseok Kim, Jeong-Gun Lee, Dong-Ik Lee	Building a Distributed Asynchronous Control Unit through Automatic Derivation of Hierarchically Decomposed AFSMs from a CDFG.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Frank Grassert, Dirk Timmermann	Dynamic single phase logic with self-timed stages for power reduction in pipeline circuit designs.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Eric Keller	Building Asynchronous Circuits with JBits.	FPL	2001	DBLP DOI BibTeX RDF
1	Mark B. Josephs, Dennis P. Furey	Delay-Insensitive Interface Specification and Synthesis.	DATE	2000	DBLP DOI BibTeX RDF
1	Vladimir Castro Alves, Felipe M. G. França, Edson do Prado Granja	A BIST Scheme for Asynchronous Logic.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	J. W. J. M. Rutten, Michel R. C. M. Berkelaar, C. A. J. van Eijk, M. A. J. Kolsteren	An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization.	DATE	1998	DBLP DOI BibTeX RDF	exact minimization, two-level minimization, hazard free logic, divide and conquer, asynchronous logic
1	Tomohiro Yoneda, Atsufumi Shibayama, Takashi Nanya	Verification of asynchronous logic circuit design using process algebra.	Systems and Computers in Japan	1997	DBLP DOI BibTeX RDF
1	David A. Kearney, Neil W. Bergmann	Bundled Data Asynchronous Multipliers with Data Dependent Computation Times.	ASYNC	1997	DBLP DOI BibTeX RDF	asynchronous logic data dependent performance multiplier
1	J. W. J. M. Rutten, Michel R. C. M. Berkelaar	Improved State Assignment for Burst Mode Finite State Machines.	ASYNC	1997	DBLP DOI BibTeX RDF	finite state machines, state assignment, asynchronous logic
1	Alain Mérigot	Associative Nets: A Graph-Based Parallel Computing Net.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	bit-serial arithmetic, graph processing, parallel algorithms, SIMD, fine grain parallelism, Parallel programming models, asynchronous logic
1	Martin Benes, Andrew Wolfe, Steven M. Nowick	A High-Speed Asynchronous Decompression Circuit for Embedded Processors.	ARVLSI	1997	DBLP DOI BibTeX RDF
1	Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni	On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic.	ASYNC	1997	DBLP DOI BibTeX RDF
1	Priyadarsan Patra, Stanislav Polonsky, Donald S. Fussell	Delay Insensitive Logic for RSFQ Superconductor Technology.	ASYNC	1997	DBLP DOI BibTeX RDF
1	Georgios K. Theodoropoulos, G. Tsakogiannis, J. V. Woods	Occam: An Asynchronous Hardware Description Language?	EUROMICRO	1997	DBLP DOI BibTeX RDF
1	Stephen B. Furber	The Return of Asynchronous Logic.	ITC	1996	DBLP DOI BibTeX RDF
1	Priyadarsan Patra, Donald S. Fussell	Efficient Delay-Insensitive RSFQ Circuits. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF
1	Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu	Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.	ISCAS	1995	DBLP BibTeX RDF
1	Branka Medved Rogina, Bozidar Vojnovic	Metastability evaluation method by propagation delay distribution measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	propagation delay distribution measurement, edge-triggered flip-flops, input signals time relationship, output signal timing characteristics, analytical representation, propagation delay density distribution function, fault events, integrated propagation delay density distribution function, flip-flop normal propagation delay, resolution time constant, automatic data acquisition, complex architecture microsystems, MTBF, latch devices, custom CMOS, VLSI, VLSI, fault diagnosis, logic testing, delays, logic design, asynchronous circuits, flip-flops, data acquisition, failure analysis, reliability analysis, graphical representation, metastability, PLD, asynchronous logic, integrated circuit reliability, statistical measurement
1	Yutaka Deguchi, Nagisa Ishiura, Shuzo Yajima	Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits.	DAC	1991	DBLP DOI BibTeX RDF
1	A. K. Burston, D. J. Kinniment, Hilary J. Kahn	A Design Language for Asynchronous Logic.	Comput. J.	1978	DBLP DOI BibTeX RDF
1	Julian R. Ullmann	An Algorithm for Subgraph Isomorphism.	J. ACM	1976	DBLP DOI BibTeX RDF
1	D. W. Lewin	Advanced Aspects of Asynchronous Logic Design.	Comput. J.	1971	DBLP DOI BibTeX RDF
1	Ernst G. Ulrich	Exclusive simulation of activity in digital networks.	Commun. ACM	1969	DBLP DOI BibTeX RDF	large systems simulation, parallel events, simultaneous activities, simulation, scheduling, digital simulation, queueing, logical simulation, network structures
1	Raymond E. Miller	A survey of asynchronous logic: Comparing various definitions and models for asynchronous switching circuits	SWCT (FOCS)	1963	DBLP DOI BibTeX RDF