Search results for "automatic test pattern generation"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Wu-Tung Cheng	Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	test logic, deep Sub-Micron technologies, scan-based ATPG, test application cost, test development, VLSI, CAD, logic testing, built-in self test, system on chip, SoC, automatic test pattern generation, automatic test pattern generation, ATPG, BIST, VLSI design, integrated circuit design, circuit CAD, VLSI testing, embedded memories, test quality, integrated circuit economics
2	Nikhil Saluja, Kanupriya Gulati, Sunil P. Khatri	SAT-based ATPG using multilevel compatible don't-cares.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Boolean satisfiabilty (SAT), testing, Automatic test pattern generation (ATPG), don't cares
2	Rolf Drechsler, Görschwin Fey	Automatic Test Pattern Generation.	SFM	2006	DBLP DOI BibTeX RDF
2	Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja	Combinational automatic test pattern generation for acyclic sequential circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
2	Pallav Gupta, Rui Zhang, Niraj K. Jha	An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks.	ICCD	2004	DBLP DOI BibTeX RDF
2	Indradeep Ghosh, Masahiro Fujita	Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
2	Zhigang Yin, Yinghua Min, Xiaowei Li	An Approach to RTL Fault Extraction and Test Generation.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF	ATPG (Automatic Test Pattern Generation), RTL (Register Transfer Level), Fault
2	Sandip Kundu	GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification.	ITC	1998	DBLP DOI BibTeX RDF
2	H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus	An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
2	Lech Józwiak	On the use of term trees for effective and efficient test pattern generation.	EUROMICRO	1997	DBLP DOI BibTeX RDF	term trees, structural automatic test pattern generation, fault discovery, structural fault model, term tree based ATPG algorithm, nonredundant faults, minimal test set, circuit redundancy, logic design, fault model, data representation, automatic test software
2	Richard M. Chou, Kewal K. Saluja	Sequential Circuit Testing: From DFT to SFT.	VLSI Design	1997	DBLP DOI BibTeX RDF	design-for-testability methods, SFT techniques, large sequential circuits, logic testing, automatic test pattern generation, ATPG, synthesis-for-testability, sequential circuit testing, DFT techniques
2	Thomas E. Marchok, Wojciech Maly	Modeling the Difficulty of Sequential Automatic Test Pattern Generation. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF
2	Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska	Fast Boolean optimization by rewiring.	ICCAD	1996	DBLP DOI BibTeX RDF	Boolean logic optimization, boolean optimization, mandatory assignments, Automatic Test Pattern Generation, automatic testing, rewiring
2	Xinghao Chen, Michael L. Bushnell	Sequential circuit test generation using dynamic justification equivalence.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	search decision spaces, test generation efficiency, automatic test pattern generation, stuck-at faults, justification
2	Xinghao Chen, Michael L. Bushnell	Generation of search state equivalence for automatic test pattern generation.	VLSI Design	1995	DBLP DOI BibTeX RDF	search state equivalence, current search status, prior search decisions, previously-searched decision spaces, enabling theorem, logic testing, integrated circuit testing, sequential circuits, automatic test pattern generation, automatic testing, search problems, sequential circuit test generation
2	Abdel-Fattah Yousif, Jun Gu	Concurrent automatic test pattern generation algorithm for combinational circuits. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	concurrent automatic test pattern generation algorithm, global computations techniques, concurrent search, ISCAS'85, ISCAS'89 benchmarks, computational complexity, logic testing, NP-hard, combinational circuits, combinational circuits, automatic testing
2	Stefan Radtke, Jens Bargfrede, Walter Anheier	Distributed automatic test pattern generation with a parallel FAN algorithm. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	distributed automatic test pattern generation, parallel FAN algorithm, backtracking mechanism, heterogeneous cluster of workstations, test vector compaction, genetic algorithms, genetic algorithm, parallel algorithms, computational complexity, logic testing, digital circuits, digital circuits, NP hard problem, sequential algorithms
2	M. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor	Compact test sets for industrial circuits.	VTS	1995	DBLP DOI BibTeX RDF	compact test sets, industrial circuits, binary logic elements, three-state elements, compaction oriented decision making, heuristics, logic testing, integrated circuit testing, automatic test pattern generation, combinational circuits, automatic testing, multivalued logic circuits, test patterns, bidirectionals, xor gates, or gates, test set size
2	Enrico Macii, Angelo R. Meo	A test generation program for sequential circuits.	J. Electronic Testing	1994	DBLP DOI BibTeX RDF	Automatic test pattern generation for sequential circuits, interactive fault simulation, pruning heuristics, circuit partitioning, testability measures
2	Karl Fuchs, Franz Fink, Michael H. Schulz	DYNAMITE: an efficient automatic test pattern generation system for path delay faults.	IEEE Trans. on CAD of Integrated Circuits and Systems	1991	DBLP DOI BibTeX RDF
2	John Giraldi, Michael L. Bushnell	EST: The New Frontier in Automatic Test-Pattern Generation.	DAC	1990	DBLP DOI BibTeX RDF
2	Michael H. Schulz, Erwin Trischler, Thomas M. Sarfert	SOCRATES: a highly efficient automatic test pattern generation system.	IEEE Trans. on CAD of Integrated Circuits and Systems	1988	DBLP DOI BibTeX RDF
1	Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara	F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG.	European Test Symposium	2011	DBLP DOI BibTeX RDF	automatic test pattern generation, scan-based test, high-level testing
1	F. Podyablonsky, N. Kascheev	Generalized faulty block model for automatic test pattern generation.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier	Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults.	VLSI Design	2010	DBLP DOI BibTeX RDF	Switching Windows, Test Set Compaction, Automatic Test Pattern Generation, Crosstalk Faults
1	Yu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang	Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Amir Zjajo, José Pineda de Gyvez	Analog Automatic Test Pattern Generation for Quasi-Static Structural Test.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, Kun-Cheng Wu	Fault modeling and testing of retention flip-flops in low power designs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Daniel Tille, Rolf Drechsler	A fast untestability proof for SAT-based ATPG.	DDECS	2009	DBLP DOI BibTeX RDF
1	Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer	Defect Aware to Power Conscious Tests - The New DFT Landscape.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Waleed K. Al-Assadi, Sindhu Kakarla	Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits.	J. Electronic Testing	2009	DBLP DOI BibTeX RDF	NULL convention logic (NCL), SCOAP, ATPG, Asynchronous circuits, Design for test (DFT)
1	Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng	Automatic Test Pattern Generation for Interconnect Open Defects.	VTS	2008	DBLP DOI BibTeX RDF	Interconnect opens, Open-via defects, ATPG
1	Daniel Tille, Rolf Drechsler	Incremental SAT Instance Generation for SAT-based ATPG.	DDECS	2008	DBLP DOI BibTeX RDF
1	Hui Liu, Huawei Li, Yu Hu, Xiaowei Li	A Scan-Based Delay Test Method for Reduction of Overtesting.	DELTA	2008	DBLP DOI BibTeX RDF	overtesting, SeBoS, delay test, IR drop
1	Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte	On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.	DFT	2008	DBLP DOI BibTeX RDF
1	Stephan Eggersglüß, Rolf Drechsler	On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults.	ISMVL	2008	DBLP DOI BibTeX RDF	Boolean Encodings, ATPG, SAT, Path Delay Faults
1	Adam B. Kinsman, Nicola Nicolici	Embedded Deterministic Test Exploiting Care Bit Clustering and Seed Borrowing.	ISQED	2008	DBLP DOI BibTeX RDF	design-for-testability, test data compression
1	Xiuqin Wang, Guangsheng Ma, Hao Wang	A Novel Method for All Solutions SAT Problem.	SNPD	2008	DBLP DOI BibTeX RDF	All Solutions, Observability Don't Cares, Circuit Structure, Boolean Satisfiability
1	Yinlei Yu, Cameron Brien, Sharad Malik	Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Manoj Kumar Goparaju, Spyros Tragoudas	A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates.	VTS	2008	DBLP DOI BibTeX RDF	Weght defects, ATPG, Threshold logic, Parametric faults
1	Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor	Test-Pattern Grading and Pattern Selection for Small-Delay Defects.	VTS	2008	DBLP DOI BibTeX RDF	Small-delay defects, pattern grading, pattern selection, ATPG
1	Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille	On Acceleration of SAT-Based ATPG for Industrial Designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Ho Fai Ko, Nicola Nicolici	Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski	Improving the Resolution of Single-Delay-Fault Diagnosis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Pallav Gupta, Rui Zhang, Niraj K. Jha	Automatic Test Generation for Combinational Threshold Logic Networks.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Shih-Chieh Wu, Chun-Yao Wang, Yung-Chih Chen	Novel Probabilistic Combinational Equivalence Checking.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Da Wang, Yu Hu, Huawei Li, Xiaowei Li	Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	microprocessor design-for-testability, built-in self-test, test generation, at-speed testing
1	Kunal P. Ganeshpure, Sandip Kundu	Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults.	DATE	2007	DBLP DOI BibTeX RDF
1	Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu	Accelerating Soft Error Rate Testing Through Pattern Selection.	IOLTS	2007	DBLP DOI BibTeX RDF	soft error rate (SER), simulation, automatic test pattern generation (ATPG), Soft error
1	Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino Bicho Dos Santos, Isabel C. Teixeira, João Paulo Teixeira	Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations.	DFT	2007	DBLP DOI BibTeX RDF
1	Nicola Nicolici, Xiaoqing Wen	Embedded Tutorial on Low Power Test.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler	SAT-based ATPG for Path Delay Faults in Sequential Circuits.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Sying-Jyan Wang, Yan-Ting Chen, Katherine Shu-Min Li	Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don't-Care Filling.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Nagesh Nagapalli	DFT and Test: Ensuring Product Quality.	ISQED	2007	DBLP DOI BibTeX RDF
1	Jacob A. Abraham, Daniel G. Saab	Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell	Zero Cost Test Point Insertion Technique for Structured ASICs.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Erik Chmelar, M. Grinchuk, Arun Gunda	Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Andrea Fedeli, Franco Fummi, Graziano Pravadelli	Properties Incompleteness Evaluation by Functional Verification.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	property coverage, Model checking, fault models, functional verification
1	Chung-Ho Chen, Chih-Kai Wei, Tai-Hua Lu, Hsun-Wei Gao	Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	S.-P. Lin, C.-L. Lee, J.-E. Chen, J.-J. Chen, K.-L. Luo, W.-C. Wu	A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Venkat Satagopan, Bonita Bhaskaran, Waleed Al-Assadi, Scott C. Smith, Sindhu Kakarla	DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker	Automatic Test Pattern Generation for Resistive Bridging Faults.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	resistive short defects, ATPG, SAT, bridging faults
1	Tiziana Gravagnoli, Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciuto	Automatic Test Pattern Generation with BOA.	PPSN	2006	DBLP DOI BibTeX RDF
1	Zhong-Zhen Wu, Shih-Chieh Chang	Multiple wire reconnections based on implication flow graph.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	global flow optimization (GFO), implication flow graph (IFG), mandatory assignment, multiple wire reconnection, redundant wire, Automatic test pattern generation (ATPG)
1	Qingwei Wu, Michael S. Hsiao	A New Simulation-Based Property Checking Algorithm Based on Partitioned Alternative Search Space Traversal.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	verification, Automatic test pattern generation (ATPG), satisfiability, logic-simulation
1	Zhaohui Fu, Sharad Malik	Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search.	ICCAD	2006	DBLP DOI BibTeX RDF	MinCostSAT, optimization, branch-and-bound, Boolean satisfiability
1	Yu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang	Efficient Boolean characteristic function for fast timed ATPG.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito	Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters.	DFT	2006	DBLP DOI BibTeX RDF
1	Martin Stáva, Ondrej Novák	Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW.	DSD	2006	DBLP DOI BibTeX RDF	FPGA, VLSI, ATPG, hardware, on-line learning, Backtrace
1	Sean Safarpour, Andreas G. Veneris, Rolf Drechsler	Integrating observability don't cares in all-solution SAT solvers.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Görschwin Fey, Junhao Shi, Rolf Drechsler	Efficiency of Multi-Valued Encoding in SAT-based ATPG.	ISMVL	2006	DBLP DOI BibTeX RDF
1	Arkan Abdulrahman, Spyros Tragoudas	Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level.	ISQED	2006	DBLP DOI BibTeX RDF
1	Shweta Chary, Michael L. Bushnell	Analog Macromodeling for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Shweta Chary, Michael L. Bushnell	Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Suresh Kumar Devanathan, Michael L. Bushnell	Sequential Spectral ATPG Using the Wavelet Transform and Compaction.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Loganathan Lingappan, Niraj K. Jha	Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Vlado Vorisek, Bruce Swanson, Kun-Han Tsai, Dhiraj Goswami	Improved Handling of False and Multicycle Paths in ATPG.	VTS	2006	DBLP DOI BibTeX RDF
1	Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha	Satisfiability-based test generation for nonseparable RTL controller-datapath circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng	Pseudofunctional testing.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Instruction-Based Self-Testing of Delay Faults in Pipelined Processors.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Shahin Nazarian, Massoud Pedram, Emre Tuncer	An empirical study of crosstalk in VDSM technologies.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	automatic test pattern generation (ATPG) tool, crosstalk induced slowdown and speedup, transition time, static timing analysis (STA), skew
1	Huawei Li, Xiaowei Li	Selection of Crosstalk-Induced Faults in Enhanced Delay Test.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	automatic test pattern generation (ATPG), crosstalk, delay test, critical paths
1	Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer	Structural search for RTL with predicate learning.	DAC	2005	DBLP DOI BibTeX RDF	learning, satisfiability, interval arithmetic, predicate abstraction
1	Kameshwar Chandrasekar, Michael S. Hsiao	Forward image computation with backtracing ATPG and incremental state-set construction.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	model checking, ATPG, image computation, ZBDDs
1	Franco Fummi, Cristina Marconcini, Graziano Pravadelli	An EFSM-based approach for functional ATPG.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	ATPG, fault models, EFSM
1	Ahmad A. Al-Yamani, Edward J. McCluskey	Test chip experimental results on high-level structural test.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	test experiment, Structural test, VLSI test, complex gates
1	Indradeep Ghosh	High Level Test Generation for Custom Hardware: An Industrial Perspective.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	Functional Verification of Networked Embedded Systems.	ISQED	2005	DBLP DOI BibTeX RDF
1	Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel	PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits.	ISVLSI	2005	DBLP DOI BibTeX RDF
1	Aniket, Ravishankar Arunachalam	Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Loganathan Lingappan, Niraj K. Jha	Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits.	VTS	2005	DBLP DOI BibTeX RDF
1	Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey	Optimized reseeding by seed ordering and encoding.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, George Xenoulis	Software-Based Self-Testing of Embedded Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	processor self-testing, Embedded processors, software-based self-testing, low-cost testing
1	Maria K. Michael, Spyros Tragoudas	Function-based compact test pattern generation for path delay faults.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen	Optimal Interconnect ATPG Under a Ground-Bounce Constraint.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	testing, interconnect, Hamming distance, wires, ground bounce
1	Feng Shi, Yiorgos Makris	SPIN-TEST: automatic test pattern generation for speed-independent circuits.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Carlos Eduardo Savioli, Claudio C. Czendrodi, José Vicente Calvano, Antonio Carneiro de Mesquita Filho	ATPG for fault diagnosis on analog electrical networks using evolutionary techniques.	SBCCI	2004	DBLP DOI BibTeX RDF	genetic algorithms, automatic test pattern generation, fault models, analog and mixed-signal test
1	Peter Wohl, John A. Waicukauski, Sanjay Patel	Scalable selector architecture for x-tolerant deterministic BIST.	DAC	2004	DBLP DOI BibTeX RDF	test-generation (ATPG), test-data compression
1	Arkan Abdulrahman, Spyros Tragoudas	Compact ATPG for Concurrent SOC Testing.	MTV	2004	DBLP DOI BibTeX RDF
1	Pan Zhongliang	Neural Network Model for Testing Stuck-at and Delay Faults in Digital Circuit.	VLSI Design	2004	DBLP DOI BibTeX RDF