Search results for "behavioral synthesis"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Mark Genoe, Paul Vanoostende, Geert van Wauwe	On the use of VHDL-based behavioral synthesis for telecom ASIC design.	ISSS	1995	DBLP DOI BibTeX RDF	Alcatel-Bell, RTL-synthesizable description, behavioral synthesis tools, hardware CAD tool, system level design methodology, telecom ASIC design, telecom system hardware design, high level synthesis, VHDL, VHDL, application specific integrated circuits, ASIC, logic synthesis, integrated circuit design, hardware description languages, integrated logic circuits, behavioral synthesis, telecommunication computing, hardware software codesign, design complexities
3	Jason Cong, Bin Liu 0006, Zhiru Zhang	Behavior-level observability don't-cares and application to low-power behavioral synthesis.	ISLPED	2009	DBLP DOI BibTeX RDF	low power, observability, behavioral synthesis
3	Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii	Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	function calls, integer programming problem, behavioral synthesis
3	Farinaz Koushanfar, Inki Hong, Miodrag Potkonjak	Behavioral synthesis techniques for intellectual property protection.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	watermarking, behavioral synthesis, Intellectual property protection
3	Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin	A memory aware behavioral synthesis tool for real-time VLSI circuits.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	memory aware, behavioral synthesis, VLSI circuits
3	Martin Speitel, Michael Schlicht, Martin Leyh	Acceleration of DAB Chipset Development by Deployment of a Real-time Rapid Prototyping Approach based on Behavioral Synthesis.	ISQED	2001	DBLP DOI BibTeX RDF	real-time rapid prototyping, behavioral synthesis, digital radio
3	Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha	Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	concurrent error detection, Behavioral synthesis, fault security, fault-tolerant microarchitectures
3	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits
2	Joachim Keinert, Martin Streubühr, Thomas Schlichter, Joachim Falk, Jens Gladigau, Christian Haubelt, Jürgen Teich, Michael Meredith	SystemCoDesigner - an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	System design, hardware/software codesign
2	Sandip Ray, Kecheng Hao, Yan Chen, Fei Xie, Jin Yang	Formal Verification for High-Assurance Behavioral Synthesis.	ATVA	2009	DBLP DOI BibTeX RDF
2	Junbo Yu, Qiang Zhou, Jinian Bian	Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Feng Wang 0004, Yuan Xie, Andrés Takach	Variation-aware resource sharing and binding in behavioral synthesis.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Vyas Krishnan, Srinivas Katkoori	Simultaneous Peak Temperature and Average Power Minimization during Behavioral Synthesis.	VLSI Design	2009	DBLP DOI BibTeX RDF
2	Jason Cong, Albert Liu, Bin Liu 0006	A variation-tolerant scheduler for better than worst-case behavioral synthesis.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	scheduling, variation, behavioral synthesis
2	Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang	Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	Tsuyoshi Sadakata, Yusuke Matsunaga	An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis.	ASP-DAC	2008	DBLP DOI BibTeX RDF
2	George Economakos	Efficient implementation of biomedical hardware using open source descriptions and behavioral synthesis.	BIBE	2008	DBLP DOI BibTeX RDF
2	Harald Obereder, Markus Pfaff	Behavioral synthesis of property specification language (PSL) assertions.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
2	Saraju P. Mohanty, Elias Kougianos	Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis.	VLSI Design	2007	DBLP DOI BibTeX RDF
2	Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii	Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study.	ICESS	2007	DBLP DOI BibTeX RDF
2	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	ILP models for simultaneous energy and transient power minimization during behavioral synthesis.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	average power, cycle difference power, datapath scheduling, dynamic frequency clocking, multicycling, multiple supply voltages, peak power differential, Peak power
2	Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada	Function Call Optimization in Behavioral Synthesis.	DSD	2006	DBLP DOI BibTeX RDF
2	George Economakos	Behavioral synthesis with SystemC and PSL assertions for interface specification.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Jason Cong, Zhiru Zhang	An efficient and versatile scheduling algorithm based on SDC formulation.	DAC	2006	DBLP DOI BibTeX RDF	scheduling, behavioral synthesis, SDC
2	Xiaoyong Tang, Tianyi Jiang, Alex K. Jones, Prithviraj Banerjee	Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy Implementation.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	Kazutoshi Wakabayashi	System LSI design with C-based behavioral synthesis and verification.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Mathew A. Sacker, Andrew D. Brown, Andrew J. Rushton, Peter R. Wilson	A behavioral synthesis system for asynchronous circuits.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
2	Saraju P. Mohanty, Nagarajan Ranganathan	A framework for energy and transient power reduction during behavioral synthesis.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
2	S. F. Nielsen, Jens Sparsø, Jan Madsen	Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation.	DSD	2004	DBLP DOI BibTeX RDF
2	Kazutoshi Wakabayashi	C-based behavioral synthesis and verification analysis on industrial design examples.	ASP-DAC	2004	DBLP DOI BibTeX RDF
2	Ashok K. Murugavel, N. Ranganathan	Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis.	VLSI Design	2004	DBLP DOI BibTeX RDF
2	Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin	Memory accesses management during high level synthesis.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	memory aware, behavioral synthesis
2	Darko Kirovski, Miodrag Potkonjak	Local watermarks: methodology and application to behavioral synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
2	Ashok K. Murugavel, N. Ranganathan	A game theoretic approach for power optimization during behavioral synthesis.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
2	Byoungro So, Pedro C. Diniz, Mary W. Hall	Using estimates from behavioral synthesis tools in compiler-directed design space exploration.	DAC	2003	DBLP DOI BibTeX RDF	synthesis techniques for reconfigurable computing, field-programmable-gate-array, high-level synthesis, rapid prototyping, design space exploration
2	Saraju P. Mohanty, N. Ranganathan	A Framework for Energy and Transient Power Reduction during Behavioral Synthesis.	VLSI Design	2003	DBLP DOI BibTeX RDF
2	Ashok K. Murugavel, N. Ranganathan	A Game-Theoretic Approach for Binding in Behavioral Synthesis.	VLSI Design	2003	DBLP DOI BibTeX RDF
2	Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason Cong	Gradual Relaxation Techniques with Applications to Behavioral Synthesis.	ICCAD	2003	DBLP DOI BibTeX RDF
2	Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi	A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs.	IWDC	2002	DBLP DOI BibTeX RDF
2	Milenko Drinic, Darko Kirovski	Behavioral synthesis via engineering change.	DAC	2002	DBLP DOI BibTeX RDF	engineering change, scheduling, transformations, register assignment
2	Chandramouli Gopalakrishnan, Srinivas Katkoori	Behavioral synthesis of datapaths with low leakage power.	ISCAS	2002	DBLP DOI BibTeX RDF
2	Jennifer L. Wong, Seapahn Megerian, Miodrag Potkonjak	Forward-looking objective functions: concept & applications in high level synthesis.	DAC	2002	DBLP DOI BibTeX RDF	scheduling, transformations, behavioral synthesis, objective functions, register assignment
2	Zaher Baidas, Andrew D. Brown, Alan Christopher Williams	Floating-point behavioral synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
2	Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer	Introducing redundant computations in RTL data paths for reducing BIST resources.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	behavioral synthesis built-in self-test, redundant operations, data flow graphs
2	William E. Dougherty, Donald E. Thomas	Unifying behavioral synthesis and physical design.	DAC	2000	DBLP DOI BibTeX RDF	behavioral/high level synthesis, physical design
2	Wander O. Cesário, Zoltan Sugar, Imed Moussa, Ahmed Amine Jerraya	Efficient Integration of Behavioral Synthesis with Existing Design Flows.	ISSS	2000	DBLP DOI BibTeX RDF
2	Wander O. Cesário, Ahmed Amine Jerraya, Zoltan Sugar, Imed Moussa	Rethinking Behavioral Synthesis for a Better Integration within Existing Design Flows. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
2	Ramesh Karri, Kyosun Kim, Miodrag Potkonjak	Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Application specific programmable processors, fault tolerance, graceful degradation, behavioral synthesis
2	Alex Doboli, Ranga Vemuri	A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems.	DATE	1999	DBLP DOI BibTeX RDF
2	Xiaowei Li, Paul Y. S. Cheung	An approach to behavioral synthesis for loop-based BIST.	ISCAS	1999	DBLP DOI BibTeX RDF
2	Preeti Ranjan Panda	Memory bank customization and assignment in behavioral synthesis.	ICCAD	1999	DBLP BibTeX RDF
2	Sandeep Bhatia, Niraj K. Jha	Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF
2	A. Jemai, Polen Kission, Ahmed Amine Jerraya	Architectural Simulation in the Context of Behavioral Synthesis.	DATE	1998	DBLP DOI BibTeX RDF
2	Sujit Dey, Anand Raghunathan, Kenneth D. Wagner	Design for Testability Techniques at the Behavioral and Register-Transfer Levels.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	behavioral synthesis for testability, behavioral synthesis for BIST, high-level test generation, RTL synthesis for testability, design for testability
2	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
2	Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre	Improving Testability of Non-Scan Designs during Behavioral Synthesis.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	behavioral level, high level synthesis, design for testability
2	Miodrag Potkonjak, Kyosun Kim, Ramesh Karri	Methodology for Behavioral Synthesis-Based Algorithm-Level Design Space Exploration: DCT Case Study.	DAC	1997	DBLP DOI BibTeX RDF
2	Herbert Dawid, Klaus-Jürgen Koch, Johannes Stahl	ADPCM codec: from system level description to versatile HDL model.	ASAP	1997	DBLP DOI BibTeX RDF	differential pulse code modulation, ADPCM codec, system level description, versatile HDL model, architectural design exploration, fast system simulation, adaptive differential pulse code modulation codec module, power analysis, design verification, behavioral synthesis, design reuse, system complexity, design constraints
2	Krzysztof Bilinski, Erik L. Dagless, Jonathan M. Saul	Behavioral Synthesis of Complex Parallel Controllers.	VLSI Design	1996	DBLP DOI BibTeX RDF
2	H. Fatih Ugurdag, Thomas E. Fuhrman	Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapath. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF	Autocircuit, clock edge general behavioral synthesis system, physical datapaths, next-generation synthesis tool, behavioral HDL input descriptions, data-flow representations, use-trees, raw-states, word-oriented synthesis, unique parameterized netlist representation, high level synthesis, high-level design
2	Richard C. Ho, Mark Horowitz	Validation coverage analysis for complex digital designs.	ICCAD	1996	DBLP DOI BibTeX RDF	interactive behavioral synthesis, clock selection
2	Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao	Easily Testable Data Path Allocation Using Input/Output Registers.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	testable data path allocation, behavioral synthesis systems, input/output registers, interconnection allocation, module allocation, higher fault coverage, lower hardware overhead, improved testability, VLSI synthesis, optimization, algorithms, benchmarks, ATPG, DFT, register allocation, circuit optimisation, RTL design
2	Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy	Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
2	Miodrag Potkonjak, Anantha Chandrakasan	Synthesis and selection of DCT algorithms using behavioral synthesis-based algorithm space exploration. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	DCT algorithms, behavioral synthesis-based algorithm space exploration, high level synthesis tools, behavioral design space, IC implementation, image processing, image processing, high level synthesis, discrete cosine transforms, discrete cosine transform, application specific integrated circuits, circuit layout CAD, video processing, fast algorithms, video signal processing, digital signal processing chips, design space
2	Jay K. Adams, Donald E. Thomas	Multiple-process behavioral synthesis for mixed hardware-software systems.	ISSS	1995	DBLP DOI BibTeX RDF	automated iterative improvement technique, concurrency optimization, concurrency tradeoffs, cost/performance ratio, hardware-software tradeoffs, mixed hardware-software systems, multiple-process behavioral synthesis, software engineering, resource allocation, concurrency control, controllers, optimisation, high level synthesis, logic design, multiprocessing systems, microprocessors, ASICs, application specific integrated circuits, ASIC, microprocessor chips, cost-benefit analysis
2	Frank Vahid	Procedure exlining: a transformation for improved system and behavioral synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	VHDL transformation tool, distinct computation, procedure exlining, procedure inlining, redundant sequences, statements, formal specification, distributed processing, VHDL, hardware description languages, remote procedure calls, behavioral synthesis, behavioral specification, system synthesis, procedure calls, synthesis tools
2	Herman Schmit, Donald E. Thomas	Array mapping in behavioral synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	array grouping, array mapping, memory components, memory design space, schedule length, scheduling, data structures, memory architecture, hardware description languages, binding, behavioral synthesis, access times, design representation, hardware synthesis, synthesis tool
2	Miodrag Potkonjak, Wayne Wolf	Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques.	ICCAD	1995	DBLP DOI BibTeX RDF	allocation algorithms, behavioral synthesis techniques, datapath synthesis criteria, multiple computational tasks, multiple-task examples, periodic hard-real time systems, real-time systems, high level synthesis, logic design, application specific integrated circuits, circuit CAD, circuit optimisation, cost optimization, rate-monotonic scheduling, task sharing, synthesis algorithm, ASIC implementation
2	Jay K. Adams, John Alan Miller, Donald E. Thomas	Execution-time profiling for multiple-process behavioral synthesis. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	execution-time profiling, multiple-process behavioral synthesis, back-annotating, source description, behavioral simulation model, annotated behavioral simulation, high level synthesis, high-level synthesis, timing, timing, logic CAD, digital simulation, circuit analysis computing, hardware design, software profiling, register-transfer level model
2	Anand Raghunathan, Niraj K. Jha	An iterative improvement algorithm for low power data path synthesis.	ICCAD	1995	DBLP DOI BibTeX RDF	Low power VLSI design, Power consumption, Behavioral synthesis
2	Huy Nguyen, Abhijit Chatterjee	OPTIMUS: a new program for OPTIMizing linear circuits with number-splitting and shift-and-add decompositions.	ARVLSI	1995	DBLP DOI BibTeX RDF	linear network synthesis, OPTIMUS program, linear circuits, shift-and-add decomposition, behavioral synthesis tool, architectural transformations, numerical matrix transformation algorithms, number-splitting transformation, optimization, high level synthesis, multiplications, circuit CAD, circuit optimisation, matrix decomposition
2	Chung-Hsing Chen, Tanay Karnik, Daniel G. Saab	Structural and behavioral synthesis for testability techniques.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
2	Hsiao-Ping Juan, Viraphol Chaiyakul, Daniel D. Gajski	Condition graphs for high-quality behavioral synthesis.	ICCAD	1994	DBLP DOI BibTeX RDF
2	Rolf Ernst, S. Sutarwala, J.-Y. Jou, M. Tong	Simulation based verification of register-transfer level behavioral synthesis tools.	EURO-DAC	1990	DBLP DOI BibTeX RDF
2	Nikil D. Dutt, Tedd Hadley, Daniel Gajski	An Intermediate Representation for Behavioral Synthesis.	DAC	1990	DBLP DOI BibTeX RDF
2	Wayne Wolf	The FSM Network Model for Behavioral Synthesis of Control-Dominated Machines.	DAC	1990	DBLP DOI BibTeX RDF
2	Nikil D. Dutt, Daniel Gajski	Designer Controlled Behavioral Synthesis.	DAC	1989	DBLP DOI BibTeX RDF
2	M. T. Trick, Stephen W. Director	LASSIE: Structure to Layout for Behavioral Synthesis Tools.	DAC	1989	DBLP DOI BibTeX RDF
2	Chia-Jeng Tseng, Ruey-Sing Wei, Steven G. Rothweiler, Michael M. Tong, Ajoy K. Bose	Bridge: A Versatile Behavioral Synthesis System.	DAC	1988	DBLP BibTeX RDF
1	Naohiro Hamada, Hiroshi Saito	Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data Implementation.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong	An integrated and automated memory optimization flow for FPGA behavioral synthesis.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Jason Cong, Hui Huang 0001, Wei Jiang	Pattern-Mining for Behavioral Synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Naohiro Hamada, Hiroshi Saito	Integration of behavioral synthesis and floorplanning for asynchronous circuits with bundled-data implementation.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Masaru Takahashi	FPGA prototyping using behavioral synthesis for improving video processing algorithm and FHD TV SoC design.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Dimitrios Amanatidis, Michael Dossis	Use of Behavioral Synthesis to Implement a Cellular Neural Network for Image Processing Applications.	Panhellenic Conference on Informatics	2011	DBLP DOI BibTeX RDF
1	Jason Cong, Bin Liu 0006, Rupak Majumdar, Zhiru Zhang	Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
1	Vyas Krishnan, Srinivas Katkoori	TABS: Temperature-Aware Layout-Driven Behavioral Synthesis.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Yibo Chen, Yuan Xie, Yu Wang 0002, Andrés Takach	Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Jason Cong, Hui Huang 0001, Wei Jiang	A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis.	DATE	2010	DBLP BibTeX RDF
1	Jason Cong, Bin Liu 0006, Junjuan Xu	Coordinated resource optimization in behavioral synthesis.	DATE	2010	DBLP BibTeX RDF
1	Kecheng Hao, Fei Xie, Sandip Ray, Jin Yang	Optimizing equivalence checking for behavioral synthesis.	DATE	2010	DBLP BibTeX RDF
1	Junbo Yu, Qiang Zhou, Gang Qu, Jinian Bian	Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation.	IEICE Transactions	2009	DBLP BibTeX RDF
1	S. F. Nielsen, Jens Sparsø, Jan Madsen	Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Florian Eibensteiner, Rainer Findenig, Markus Pfaff	SynPSL: Behavioral Synthesis of PSL Assertions.	EUROCAST	2009	DBLP DOI BibTeX RDF	Synthesis, PSL, Assertion-based Verification
1	Jason Cong, Yiping Fan, Junjuan Xu	Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	distributed register file, Behavioral synthesis, resource binding
1	Ali Dasdan	Provably efficient algorithms for resolving temporal and spatial difference constraint violations.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	interface timing, layout compaction, scheduling, real-time systems, constraint satisfaction, timing constraints, Behavioral synthesis, multimedia synchronization, rate analysis
1	Saraju P. Mohanty	Unified Challenges in Nano-CMOS High-Level Synthesis.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Javier Melenchón, Elisa Martínez, Fernando De la Torre, José A. Montero	Emphatic Visual Speech Synthesis.	IEEE Transactions on Audio, Speech & Language Processing	2009	DBLP DOI BibTeX RDF
1	Frank Hannig, Hritam Dutta, Jürgen Teich	Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning.	ARCS	2009	DBLP DOI BibTeX RDF
1	Tsuyoshi Sadakata, Yusuke Matsunaga	A Behavioral Synthesis Method with Special Functional Units.	IEICE Transactions	2008	DBLP DOI BibTeX RDF