Search results for "behavioural synthesis"

Found 12 publication records. Showing 12 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	M. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter Kollig	Design of a low power MPEG-1 motion vector reconstructor.	SBCCI	2009	DBLP DOI BibTeX RDF	behavioural synthesis, low power
2	M. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter Kollig	Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Mathew A. Sacker, Andrew D. Brown, Peter R. Wilson, Andrew J. Rushton	A General Purpose Behavioural Asynchronous Synthesis System.	ASYNC	2004	DBLP DOI BibTeX RDF	Behavioural synthesis, asynchronous synthesis, cryptography
2	Ali E. Abdallah, John Hawkins	Formal Behavioural Synthesis of Handel-C Parallel Hardware Implementations from Functional Specifications. (PDF / PS)	HICSS	2003	DBLP DOI BibTeX RDF
2	Ahmed Hemani, Adam Postula	A neural net based self organising scheduling algorithm.	EURO-DAC	1990	DBLP DOI BibTeX RDF	Behavioural Synthesis, Scheduling, Neural Nets, Self Organisation, Optimisation Techniques
1	Sven Rosinger, Kiril Schröder, Wolfgang Nebel	Power Management Aware Low Leakage Behavioural Synthesis.	DSD	2009	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Elias Kougianos, Dhiraj K. Pradhan	Simultaneous scheduling and binding for low gate leakage nano-complementary metaloxide-semiconductor data path circuit behavioural synthesis.	IET Computers & Digital Techniques	2008	DBLP DOI BibTeX RDF
1	M. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter Kollig	Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	M. Hillers, W. Nebel	Impact of Array Data Flow Analysis on the Design of Energy-Efficient Circuits.	PATMOS	2006	DBLP DOI BibTeX RDF
1	M. S. Gaur, Mark Zwolinski	Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	David J. Mallon, Peter B. Denyer	A new approach to pipeline optimisation.	EURO-DAC	1990	DBLP DOI BibTeX RDF
1	Jayaram Bhasker	Process-graph Analyser: A Front-end Tool for VHDL Behavioural Synthesis.	Softw., Pract. Exper.	1988	DBLP DOI BibTeX RDF

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