Search results for "bit width"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Adam B. Kinsman, Nicola Nicolici	Robust design methods for hardware accelerators for iterative algorithms in scientific computing.	DAC	2010	DBLP DOI BibTeX RDF	bit-width allocation, satisfiability-modulo theory
2	Timothy F. Beatty, Eric E. Aubanel, Kenneth B. Kent	Customizable bit-width in an OpenMP-based circuit design tool.	FPGA	2009	DBLP DOI BibTeX RDF	handelc, hardware specification, openmp
2	Emre Özer, Andy Nisbet, David Gregg	A stochastic bitwidth estimation technique for compact and low-power custom processors.	ACM Trans. Embedded Comput. Syst.	2008	DBLP DOI BibTeX RDF	Bit-width analysis, custom hardware, FPGA, statistical estimation, extreme value theory
2	Dong-U Lee, John D. Villasenor	A Bit-Width Optimization Methodology for Polynomial-Based Function Evaluation.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	elementary function approximation, finite wordlength effects, minimax approximation and algorithms, field programmable gate arrays, Computer arithmetic
2	Benny Thörnberg, Martin Palkovic, Qubo Hu, Leif Olsson, Per Gunnar Kjeldsberg, Mattias O'Nils, Francky Catthoor	Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou	Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau	Compilation framework for code size reduction using reduced bit-width ISAs (rISAs).	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	codesize reduction, dual instruction set, narrow bit-width instruction set, rISA, register pressure-based code generation, thumb, optimization, compilers, Code generation, code compression, retargetable compilers
2	Caaliph Andriamisaina, Bertrand Le Gal, Emmanuel Casseau	Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems.	SiPS	2006	DBLP DOI BibTeX RDF
2	Yu Pu, Yajun Ha	An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model.	ASP-DAC	2006	DBLP DOI BibTeX RDF
2	Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou	Smart bit-width allocation for low power optimization in a systemc based ASIC design environment.	DATE	2006	DBLP DOI BibTeX RDF
2	Benny Thörnberg, Mattias O'Nils	Impact of bit-width specification on the memory hierarchy for a real-time video processing system.	DATE	2006	DBLP DOI BibTeX RDF
2	Jongsun Park, Jung Hwan Choi, Kaushik Roy	Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off.	DATE	2006	DBLP DOI BibTeX RDF
2	Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk	MiniBit: bit-width optimization via affine arithmetic.	DAC	2005	DBLP DOI BibTeX RDF	bit-width, simulated, FPGA, fixed-point, affine arithmetic, annealing
2	Rony Ghattas, Alexander G. Dean	Energy management for commodity short-bit-width microcontrollers.	CASES	2005	DBLP DOI BibTeX RDF	dynamic frequency scaling, short-bit-width microcontroller, embedded systems, dynamic voltage scaling, energy modeling
2	Gang Quan, James P. Davis, Siddhaveerasharan Devarkal, Duncan A. Buell	High-level synthesis for large bit-width multipliers on FPGAs: a case study.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	FPGA devices, large-scale integer multipliers, high level synthesis, reconfigurable computing, design exploration
2	Aviral Shrivastava, Nikil D. Dutt	Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA).	ASP-DAC	2004	DBLP DOI BibTeX RDF
2	Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung	Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs.	FCCM	2004	DBLP DOI BibTeX RDF
2	Emre Özer, Andy Nisbet, David Gregg	Stochastic Bit-Width Approximation Using Extreme Value Theory for Customizable Processors.	CC	2004	DBLP DOI BibTeX RDF
2	Vasily G. Moshnyaga, Koji Inoue, Mizuka Fukagawa	Reducing energy consumption of video memory by bit-width compression.	ISLPED	2002	DBLP DOI BibTeX RDF	bitwidth-compression, frame memory, low-power design
2	David Cachera, Tanguy Risset	Advances in Bit Width Selection Methodology.	ASAP	2002	DBLP DOI BibTeX RDF
2	Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi	A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design .	ISSS	2002	DBLP DOI BibTeX RDF	compressed instruction set, dual Instruction set, rISA, reduced bit-width instruction set, thumb, design space exploration, register pressure
1	Fabrizio Lamberti, Nikolaos Andrikos, Elisardo Antelo, Paolo Montuschi	Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Adam B. Kinsman, Nicola Nicolici	Automated Range and Precision Bit-Width Allocation for Iterative Computations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Mathias Faust, Chip-Hong Chang	Low error bit width reduction for structural adders of FIR filters.	ECCTD	2011	DBLP DOI BibTeX RDF
1	Adam B. Kinsman, Nicola Nicolici	Computational Vector-Magnitude-Based Range Determination for Scientific Abstract Data Types.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	Bit-width allocation, hardware accelerators
1	Adam B. Kinsman, Nicola Nicolici	Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Jongsun Park, Jung Hwan Choi, Kaushik Roy	Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa	Compiling for Reduced Bit-Width Queue Processors.	Signal Processing Systems	2010	DBLP DOI BibTeX RDF
1	Chung-Fu Lin, Pei-Kung Huang, Bing-Fei Wu	An Efficient Pipeline Architecture and Memory Bit-Width Analysis for Discrete Wavelet Transform of the 9/7 Filter for JPEG 2000.	Signal Processing Systems	2010	DBLP DOI BibTeX RDF
1	Ioannis Koutras, Antonis Papanikolaou, George Economakos, Dimitrios Soudris	BIT-width exploration over 3D architectures using high-level synthesis.	ICECS	2010	DBLP DOI BibTeX RDF
1	Yongsoon Lee, Younhee Choi, Moon Ho Lee, Seok-Bum Ko	Performance Analysis of Bit-Width Reduced Floating-Point Arithmetic Units in FPGAs: A Case Study of Neural Network-Based Face Detector.	EURASIP J. Emb. Sys.	2009	DBLP DOI BibTeX RDF
1	O. Sarbishei, M. Tabandeh, Bijan Alizadeh, Masahiro Fujita	High-level optimization of integer multipliers over a finite bit-width with verification capabilities.	MEMOCODE	2009	DBLP DOI BibTeX RDF
1	Adam B. Kinsman, Nicola Nicolici	Finite Precision bit-width allocation using SAT-Modulo Theory.	DATE	2009	DBLP BibTeX RDF
1	Robert Brummayer, Armin Biere	Effective Bit-Width and Under-Approximation.	EUROCAST	2009	DBLP DOI BibTeX RDF
1	Adam B. Kinsman, Nicola Nicolici	Computational bit-width allocation for operations in vector calculus.	ICCD	2009	DBLP DOI BibTeX RDF
1	Sudhanshu Khanna, Benton H. Calhoun	Serial sub-threshold circuits for ultra-low-power systems.	ISLPED	2009	DBLP DOI BibTeX RDF	bit width, serial systems, leakage, ultra low power, sub-threshold
1	Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa	Compiler Support for Code Size Reduction Using a Queue-Based Processor.	T. HiPEAC	2009	DBLP DOI BibTeX RDF	Reduced bit-width Instruction Set, Queue Computation Model, Code Generation, Code Size Reduction
1	Diego F. Sánchez, Daniel M. Muñoz, Carlos H. Llanos, Mauricio Ayala-Rincón	Parameterizable floating-point library for arithmetic operations in FPGAs.	SBCCI	2009	DBLP DOI BibTeX RDF	goldschmidt, FPGA, computer arithmetic, floating-point
1	Kai Zhang, Xinming Huang, Zhongfeng Wang	An Area-Efficient LDPC Decoder Architecture and Implementation for CMMB Systems.	ASAP	2009	DBLP DOI BibTeX RDF
1	Ge Zhang, Xu Yang, Yiwei Zhang	Architecture Level Energy Modeling and Optimization for Multi-Ported Giga-Hz Physical Register File.	NAS	2009	DBLP DOI BibTeX RDF
1	Tso-Bing Juang	Low Latency Angle Recoding Methods for the Higher Bit-Width Parallel CORDIC Rotator Implementations.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Yu Pang, Katarzyna Radecka	Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transform.	DAC	2008	DBLP DOI BibTeX RDF	DSP circuit synthesis, optimization, error analysis, Taylor Series
1	Jason Cong, Wei Jiang	Pattern-based behavior synthesis for FPGA resource reduction.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, pattern, behavior synthesis
1	Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty	Power-aware SoC test planning for effective utilization of port-scalable testers.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	port-scalable testers, test access architecture, integer linear programming, SoC test
1	David B. Thomas, Wayne Luk	Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware.	TRETS	2008	DBLP DOI BibTeX RDF	FPGA, Random numbers, multivariate Gaussian distribution
1	Ralf König, Timo Stripf, Jürgen Becker	A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms.	DATE	2008	DBLP DOI BibTeX RDF
1	Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner	Coarse-grained reconfiguration.	FPL	2008	DBLP DOI BibTeX RDF
1	Tso-Bing Juang, Sheng-Hung Chen, Shin-Mao Li	A novel VLSI iterative divider architecture for fast quotient generation.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Minhyeok Shin, Hanho Lee	A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Qiang Wang, Xiaofeng Tao, Ping Zhang 0003, Shu Jing	Low Complexity Hardware Implementation of V-BLAST Receiver.	VTC Spring	2008	DBLP DOI BibTeX RDF
1	Zdenek Vasícek, Martin Zádník, Lukás Sekanina, Jirí Tobola	On Evolutionary Synthesis of Linear Transforms in FPGA.	ICES	2008	DBLP DOI BibTeX RDF
1	William G. Osborne, Ray C. C. Cheung, José Gabriel F. Coutinho, Wayne Luk, Oskar Mencer	Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems.	FPL	2007	DBLP DOI BibTeX RDF
1	Nicola E. L'Insalata, Sergio Saponara, Luca Fanucci, Pierangelo Terreni	Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems.	DSD	2007	DBLP DOI BibTeX RDF
1	Haohuan Fu, Oskar Mencer, Wayne Luk	Optimizing Logarithmic Arithmetic on FPGAs.	FCCM	2007	DBLP DOI BibTeX RDF
1	Graeme Stewart, David Renshaw, Martyn Riley	A novel motion estimation power reduction technique.	FPL	2007	DBLP DOI BibTeX RDF
1	Joonhyuk Yoo, Manoj Franklin	Prioritizing verification via value-based correctness criticality.	ICCD	2007	DBLP DOI BibTeX RDF
1	Levent Aksoy, Ece Olcay Günes, Eduardo A. C. da Costa, Paulo F. Flores, José C. Monteiro	Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications.	SiPS	2007	DBLP DOI BibTeX RDF
1	Georges G. E. Gielen, Donatella Sciuto	Guest Editorial [intro. to the special issue on the 2006 IEEE/ACM Design, Automation and Test in Europe Conference].	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Dong-U Lee, Ray C. C. Cheung, John D. Villasenor	A Flexible Architecture for Precise Gamma Correction.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Jeong-Gun Lee, Jeong-A. Lee, Byeong-Seok Lee, Milos D. Ercegovac	A Design Method for Heterogeneous Adders.	ICESS	2007	DBLP DOI BibTeX RDF
1	Prassanna Sithambaram, Alberto Macii, Enrico Macii	New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses.	PATMOS	2007	DBLP DOI BibTeX RDF
1	Yulai Zhao, Xianfeng Li, Dong Tong, Xu Cheng	An Energy-Efficient Instruction Scheduler Design with Two-Level Shelving and Adaptive Banking.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	content associative memory (CAM), tag elimination, waiting instruction buffer, instruction scheduler, energy-efficient architecture
1	Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides	Accuracy-Guaranteed Bit-Width Optimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Wonwoo Jang, Hyunsik Kim, Sungmok Lee, Jooyoung Ha, Bongsoon Kang	Implementation of the Gamma Line System Similar to Non-linear Gamma Curve with 2bit Error(LSB).	APCCAS	2006	DBLP DOI BibTeX RDF
1	Tso-Bing Juang	Area/Delay Efficient Recoding Methods for Parallel CORDIC Rotations.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Chao-Huang Wei, Hsiang-Chieh Hsiao, Su-Wei Tsai	Design and Implementation of Multi-Channel Bandpass Filter for Embedded System.	DELTA	2006	DBLP DOI BibTeX RDF	FPGA, MATLAB, Co-Design, Multi-Channel, IIR filter, Bandpass filter
1	Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones	Design space exploration for low-power reconfigurable fabrics.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Hong-An Huang, Yen-Chin Liao, Hsie-Chia Chang	A self-compensation fixed-width booth multiplier and its 128-point FFT applications.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Jean-Marc Philippe, Sébastien Pillement, Olivier Sentieys	Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects.	ISQED	2006	DBLP DOI BibTeX RDF
1	Xiao Li, Jonathan Malkin, Jeff A. Bilmes	A high-speed, low-resource ASR back-end based on custom arithmetic.	IEEE Transactions on Audio, Speech & Language Processing	2006	DBLP DOI BibTeX RDF
1	Dong-U Lee, John D. Villasenor, Wayne Luk, Philip Heng Wai Leong	A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	elementary function approximation, minimax approximation and algorithms, simulation, optimization, field programmable gate arrays, computer arithmetic, error analysis, random number generation, Algorithms implemented in hardware
1	Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham	Constructing zero-deficiency parallel prefix adder of minimum depth.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy	Microarchitectural Wire Management for Performance and Power in Partitioned Architectures.	HPCA	2005	DBLP DOI BibTeX RDF
1	Masaaki Kondo, Hiroshi Nakamura	A Small, Fast and Low-Power Register File by Bit-Partitioning.	HPCA	2005	DBLP DOI BibTeX RDF
1	Yi Wang, Jussipekka Leiwo, Thambipillai Srikanthan	Efficient high radix modular multiplication for high-speed computing in re-configurable hardware [cryptographic applications].	ISCAS	2005	DBLP DOI BibTeX RDF
1	R. Gopalakrishnan, Rajat Moona	Variable Resizing for Area Improvement in Behavioral Synthesis.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk	Optimizing Hardware Function Evaluation.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	elementary function approximation, minimax approximation and algorithms, optimization, Computer arithmetic, gate arrays
1	Yu-Wen Huang, Bing-Yu Hsieh, Tung-Chien Chen, Liang-Gee Chen	Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder.	IEEE Trans. Circuits Syst. Video Techn.	2005	DBLP DOI BibTeX RDF
1	Hua Yang, Gang Cui, Xiao-Zong Yang	2L-MuRR: A Compact Register Renaming Scheme for SMT Processors.	ISPA	2005	DBLP DOI BibTeX RDF
1	Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris	Fast adders in modern FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF
1	Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee	Macro-models for high level area and power estimation on FPGAs.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	model, FPGA, high-level synthesis, power estimation, RTL, area estimation
1	Jayapreetha Natesan, Damu Radhakrishnan	Shift Invert Coding (SINV) for Low Power VLSI.	DSD	2004	DBLP DOI BibTeX RDF
1	Gerardo Leyva, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz	A Generator of High-Speed Floating-Point Modules.	FCCM	2004	DBLP DOI BibTeX RDF
1	Peter Caputa, Henrik Fredriksson, Martin Hansson, Stefan Andersson, Atila Alvandpour, Christer Svensson	An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies.	PATMOS	2004	DBLP DOI BibTeX RDF
1	G. N. Mangalam, Sanjiv Narayan, Paul van Besouw, LaNae J. Avra, Anmol Mathur, Sanjeev Saluja	Graph Transformations for Improved Tree Height Reduction.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Tom Van Court, Martin C. Herbordt, Richard J. Barton	Case Study of a Functional Genomics Application.	FPL	2003	DBLP DOI BibTeX RDF
1	Toshihito Fujiwara, Kenji Fujimoto, Tsutomu Maruyama	A Real-Time Visualization System for PIV.	FPL	2003	DBLP DOI BibTeX RDF
1	Vasily G. Moshnyaga	Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	bit-truncation, low-power design, video processing, switching activity
1	Vasily G. Moshnyaga	Reducing energy dissipation of frame memory by adaptive bit-width compression.	IEEE Trans. Circuits Syst. Video Techn.	2002	DBLP DOI BibTeX RDF
1	Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil D. Dutt, Alexandru Nicolau	An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs.	DATE	2002	DBLP DOI BibTeX RDF
1	Per Bjuréus, Mikael Millberg, Axel Jantsch	FPGA resource and timing estimation from Matlab execution traces.	CODES	2002	DBLP DOI BibTeX RDF	FPGA, estimation, Matlab, MATLAB, design exploration
1	Gabriel H. Loh	Exploiting data-width locality to increase superscalar execution bandwidth.	MICRO	2002	DBLP DOI BibTeX RDF
1	Atlaf Ul Amin, Satoshi Ohtake, Hideo Fujiwara	Design for Two-Pattern Testability of Controller-Data Path Circuits.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
1	Yan Wang, Hing Mo Lam, Chi-Ying Tsui, Roger S. Cheng, Wai Ho Mow	Low complexity OFDM receiver using Log-FFT for coded OFDM system.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Insik Shin, Insup Lee, Sang Lyul Min	Embedded System Design Framework for Minimizing Code Size and Guaranteeing Real-Time Requirements. (PDF / PS)	IEEE Real-Time Systems Symposium	2002	DBLP DOI BibTeX RDF
1	Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	Area/delay estimation for digital signal processor cores.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino	Parameterized RTL power models for soft macros.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha	TAO: regular expression-based register-transfer level testability analysis and optimization.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Tsutomu Maruyama, Tsutomu Hoshino	A C to HDL Compiler for Pipeline Processing on FPGAs.	FCCM	2000	DBLP DOI BibTeX RDF
1	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik	A BIST scheme for RTL circuits based on symbolic testabilityanalysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF