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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 3 occurrences of 3 keywords
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Results
Found 3 publication records. Showing 3 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 2 | Jason Cong, Cheng-Kok Koh |
Interconnect layout optimization under higher-order RLC model.  |
ICCAD  |
1997 |
DBLP DOI BibTeX RDF |
RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization |
| 1 | Jason Cong, Cheng-Kok Koh, Patrick H. Madden |
Interconnect layout optimization under higher order RLC model forMCM designs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
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| 1 | Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo |
Interconnect design for deep submicron ICs. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
required-arrival-time Steiner tree higher-order moment signal delay and integrity |
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