Search results for "branch target buffer"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Ioana Burcea, Andreas Moshovos	Phantom-BTB: a virtualized branch target buffer design.	ASPLOS	2009	DBLP DOI BibTeX RDF	predictor metadata prefetching, predictor virtualization, branch target buffer
2	Giovanni Agosta, Luca Breveglieri, Gerardo Pelosi, Israel Koren	Countermeasures against Branch Target Buffer Attacks.	FDTC	2007	DBLP DOI BibTeX RDF
2	Kaveh Jokar Deris, Amirali Baniasadi	Branchless cycle prediction for embedded processors.	SAC	2006	DBLP DOI BibTeX RDF	low-power design, embedded processors, branch target buffer, power-aware architectures
2	Tao Li, Ravi Bhargava, Lizy Kurian John	Adapting branch-target buffer to improve the target predictability of java code.	TACO	2005	DBLP DOI BibTeX RDF	branch-target buffer (BTB), Java, Computer architecture, branch prediction, pipelined processor
2	Peter Petrov, Alex Orailoglu	Low-power Branch Target Buffer for Application-Specific Embedded Processors.	DSD	2003	DBLP DOI BibTeX RDF
2	Tao Li, Ravi Bhargava, Lizy Kurian John	Rehashable BTB: An Adaptive Branch Target Buffer to Improve the Target Predictability of Java Code.	HiPC	2002	DBLP DOI BibTeX RDF
2	Weiyu Tang, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta	Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption.	ISHPC	2002	DBLP BibTeX RDF
2	Oliverio J. Santana, Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramírez, Mateo Valero	A Comprehensive Analysis of Indirect Branch Prediction.	ISHPC	2002	DBLP BibTeX RDF	indirect branch, Multi-Stage Cascaded Predictor, branch prediction, microarchitecture, Branch Target Buffer
2	Steven Wallace, Nader Bagherzadeh	Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors.	IEEE Trans. Parallel Distrib. Syst.	1998	DBLP DOI BibTeX RDF	performance analysis, Computer architecture, instruction fetching, branch target buffer, superscalar microprocessor
2	James O. Bondi, Ashwini K. Nanda, Simonjit Dutta	Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline.	MICRO	1996	DBLP BibTeX RDF	branch target buffer technology, deep pipelines, misprediction recovery cache integration, performance loss, residual misprediction penalty, superscalar pipeline, microprocessor chips, microprocessor designs, CISC, multiple instructions
2	Shlomit S. Pinter, Adi Yoaz	Tango: A Hardware-Based Data Prefetching Technique for Superscalar Processors.	MICRO	1996	DBLP BibTeX RDF	LRU mechanism, SPEC92 benchmark, Tango, base line architecture, hardware-based data prefetching technique, memory reference instructions, program progress graph, performance, parallel processing, instruction level parallelism, simulation results, superscalar processors, branch target buffer, instruction prefetching, hardware resources, slack time
2	Chris H. Perleberg, Alan Jay Smith	Branch Target Buffer Design and Optimization.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	branch target buffer design, branch tag, prediction information, branch target address, optimization, complexity, caching, pipeline processing, buffer storage, instructions, instruction sets, pipelined processors, branches, performance penalty, least recently used
1	Shuai Wang, Jie S. Hu, Sotirios G. Ziavras	Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures.	IET Computers & Digital Techniques	2012	DBLP DOI BibTeX RDF
1	Nadav Levison, Shlomo Weiss	Branch target buffer design for embedded processors.	Microprocessors and Microsystems - Embedded Hardware Design	2010	DBLP DOI BibTeX RDF
1	Stephen Roderick Hines, Yuval Peress, Peter Gavin, David B. Whalley, Gary S. Tyson	Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE).	LCTES	2009	DBLP DOI BibTeX RDF	l0/filter cache, lookahead instruction fetch engine (life), tagless hit instruction cache (th-ic)
1	Christos Strydis, Georgi Gaydadjiev	Evaluating Various Branch-Prediction Schemes for Biomedical-Implant Processors.	ASAP	2009	DBLP DOI BibTeX RDF
1	Vladimir Uzelac, Aleksandar Milenkovic	Experiment flows and microbenchmarks for reverse engineering of branch predictor structures.	ISPASS	2009	DBLP DOI BibTeX RDF
1	José A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, Yale N. Patt	Improving the performance of object-oriented languages with dynamic predication of indirect jumps.	ASPLOS	2008	DBLP DOI BibTeX RDF	dynamic predication, indirect jumps, object-oriented languages, predicated execution, virtual functions
1	Hans Vandierendonck, André Seznec	Speculative return address stack management revisited.	TACO	2008	DBLP DOI BibTeX RDF	Return address prediction, back-up predictor, corruption detection
1	Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow	A Desktop Computer with a Reconfigurable Pentium®.	TRETS	2008	DBLP DOI BibTeX RDF	Pentium®, simulator, model, FPGA, architecture, operating system, reconfigurable, emulator, exploration, accelerator, processor
1	Juan Carlos Martinez Santos, Yunsi Fei	Leveraging speculative architectures for run-time program validation.	ICCD	2008	DBLP DOI BibTeX RDF
1	Kevin Casey, M. Anton Ertl, David Gregg	Optimizing indirect branch prediction accuracy in virtual machine interpreters.	ACM Trans. Program. Lang. Syst.	2007	DBLP DOI BibTeX RDF	code replication, superinstruction, Interpreter, branch prediction, branch target buffer
1	Shih-Lien Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh	An FPGA-based Pentium in a complete desktop system.	FPGA	2007	DBLP DOI BibTeX RDF	pentium®, FPGA, emulator, accelerator, processor
1	Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn	VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization.	ISCA	2007	DBLP DOI BibTeX RDF	devirtualization, indirect branch prediction, virtual functions
1	Yixin Shi, Gyungho Lee	Augmenting Branch Predictor to Secure Program Execution.	DSN	2007	DBLP DOI BibTeX RDF	Control Flow Validation, Indirect Branch, Bloom Filter, Software Protection, Branch Predictor
1	Kiran Puttaswamy, Gabriel H. Loh	Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors.	HPCA	2007	DBLP DOI BibTeX RDF
1	Fei Gao, Suleyman Sair	Exploiting Intra-function Correlation with the Global History Stack.	SAMOS	2005	DBLP DOI BibTeX RDF
1	Cheol Kim, Sung Chung, Chu Shik Jhon	A Power-Aware Branch Predictor by Accessing the BTB Selectively.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	BTB, PHT, low power design, embedded processor, branch predictor
1	Hidenori Sato, Toshinori Sato	A static and dynamic energy reduction technique for I-cache and BTB in embedded processors.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Philo Juang, Kevin Skadron, Margaret Martonosi, Zhigang Hu, Douglas W. Clark, Phil Diodato, Stefanos Kaxiras	Implementing branch-predictor decay using quasi-static memory cells.	TACO	2004	DBLP DOI BibTeX RDF	Energy aware computing
1	Dharmesh Parikh, Kevin Skadron, Yan Zhang, Mircea R. Stan	Power-Aware Branch Prediction: Characterization and Design.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	target prediction, highly-biased branches, pipeline gating, speculation control, Low-power design, power, branch prediction, processor architecture, energy-aware systems, banking
1	Sung Woo Chung, Sung-Bae Park	A Low Power Branch Predictor to Selectively Access the BTB.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
1	Weidong Shi, Tao Zhang, Santosh Pande	Static Techniques to Improve Power Efficiency of Branch Predictors.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
1	Tao Zhang, Weidong Shi, Santosh Pande	Static Techniques to Improve Power Efficiency of Branch Predictors.	HiPC	2004	DBLP DOI BibTeX RDF
1	M. Anton Ertl, David Gregg	Optimizing indirect branch prediction accuracy in virtual machine interpreters.	PLDI	2003	DBLP DOI BibTeX RDF	code replication, superinstruction, interpreter, branch prediction, branch target buffer
1	Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang	Branch prediction on demand: an energy-efficient solution.	ISLPED	2003	DBLP DOI BibTeX RDF	adaptive, profiling, branch prediction
1	Enric Musoll	Speculating to reduce unnecessary power consumption.	ACM Trans. Embedded Comput. Syst.	2003	DBLP DOI BibTeX RDF	low-power microarchitectures, Low-power design
1	Nick Richardson, Lun Bin Huang, Razak Hossain, Tommy Zounes, Naresh Soni, Julian Lewis	The iCOREtm 520 MHz synthesizable CPU core.	DAC	2002	DBLP DOI BibTeX RDF	high-frequency, st20, cache, synthesis, pipeline, embedded, ASIC, branch-prediction, microarchitecture, CPU
1	Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami	A history-based I-cache for low-energy multimedia applications.	ISLPED	2002	DBLP DOI BibTeX RDF
1	Zhigang Hu, Philo Juang, Kevin Skadron, Douglas W. Clark, Margaret Martonosi	Applying Decay Strategies to Branch Predictors for Leakage Energy Savings.	ICCD	2002	DBLP DOI BibTeX RDF
1	Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti	Minimizing Energy Consumption for High-Performance Processing.	VLSI Design	2002	DBLP DOI BibTeX RDF	BTB size, voltage reduction, frequency reduction, parallel processing, low power, energy savings, MPEG-2, cache size
1	Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami	Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints.	PACS	2002	DBLP DOI BibTeX RDF
1	Yul Chu, Mabo Robert Ito	An Efficient Indirect Branch Predictor.	Euro-Par	2001	DBLP DOI BibTeX RDF
1	Matthew C. Merten, Andrew R. Trick, Erik M. Nystrom, Ronald D. Barnes, Wen-mei W. Hwu	A hardware mechanism for dynamic extraction and relayout of program hot spots.	ISCA	2000	DBLP DOI BibTeX RDF
1	Enric Musoll	Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors. (PDF / PS)	MICRO	1999	DBLP DOI BibTeX RDF
1	Barry S. Fagin	Partial Resolution in Branch Target Buffers.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	computer architecture, cache memory, Branch prediction, microarchitecture, branch target buffer
1	André Seznec	Don't Use the Page Number, But a Pointer To It.	ISCA	1996	DBLP DOI BibTeX RDF	address width, indirect-tagged caches, reduced branch target buffers, tag implementation cost
1	Robert Yung	Design Decisions Influencing the UltraSPARC's Instruction Fetch Architecture.	MICRO	1996	DBLP DOI BibTeX RDF	UltraSPARC, fast cycle time, in-cache prediction, instruction fetch architecture, instruction fetch unit, lower cycle-per-instruction, predictive set-associative cache, prefetch and dispatch unit, trade-off decisions, computer architecture, microprocessor
1	Yue Liu, David R. Kaeli	Branch-Directed and Stride-Based Data Cache Prefetching. (PDF / PS)	ICCD	1996	DBLP DOI BibTeX RDF
1	Steven Wallace, Nader Bagherzadeh	Instruction Fetching Mechanisms for Superscalar Microprocessors.	Euro-Par, Vol. II	1996	DBLP DOI BibTeX RDF
1	Weili Chu, Stamatis Vassiliadis, José G. Delgado-Frias	The multi-associative branch target buffer: a cost effective BTB mechanism.	Microprocessing and Microprogramming	1995	DBLP DOI BibTeX RDF
1	Barry S. Fagin, Amit Mital	The Performance of Counter- and Correlation-Based Schemes for Branch Target Buffers.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	Branch correlation, performance modeling, branch prediction, trace-driven simulation, branch target buffer
1	Pradeep K. Dubey, Michael J. Flynn	Branch Strategies: Modeling and Optimization.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	branch-delay penalty, instruction bandwidth, i-traffic, wasted instruction fetches, active branch prediction, loop buffers, parallel programming, compilers, program compilers, pipeline processing, pipelined processors, branch-target-buffer
1	Johnny F. K. Lee, Alan Jay Smith	Branch Prediction Strategies and Branch Target Buffer Design.	IEEE Computer	1984	DBLP DOI BibTeX RDF
1	Johnny K. F. Lee, A. J. Smith	Analysis of branch prediction strategies and branch target buffer design.	Perform. Eval.	1983	DBLP DOI BibTeX RDF